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? 2015 microchip technology inc. ds00001913a-page 1 highlights 16-bit 10/100 industrial ethernet controller & phy interfaces to most 8/16-bit embedded controllers and 32-bit embedded controllers with an 8/16-bit bus integrated ethernet phy with hp auto-mdix integrated ethernet mac compliant with energy efficient ethernet 802.3az wake on lan (wol) support integrated ieee 1588v2 hardware time stamp unit cable diagnostic support 1.8v to 3.3v variable voltage i/o integrated 1.2v regulator for single 3.3v operation low pin count and small body size package target applications cable, satellite, an d ip set-top boxes digital televisions & video recorders voip/video phone systems home gateways test/measurement equipment industrial aut omation systems key benefits single-chip ethernet controller - fully compliant with ieee 802.3/802.3u standards - integrated ethernet mac and phy - 10base-t and 100base-tx support - 100base-fx support for external fiber transceiver - automatic polarity detection and correction (hp auto-mdix) - full- and half-duplex support - full-duplex flow control - backpressure for half-duplex flow control - preamble generation and removal - automatic 32-bit crc generation and checking - automatic payload padding and pad removal - loop-back modes eliminates dropped packets - internal buffer memory can store over 200 packets - automatic pause and back-pressure flow control flexible address filtering modes - one 48-bit perfect address - 64 hash-filtered multicast addresses - pass all multicast - promiscuous mode - inverse filtering - pass all incoming with status report - disable reception of broadcast packets 8/16-bit host bus interface - indexed register or multiplexed bus - 16kbyte fifo with flexible tx/rx allocation - spi / quad spi support ieee 1588v2 hardware time stamp unit - global 64-bit tunable clock - ordinary clock: master / slave, one-step / two-step, end- to-end / peer-to-peer delay - fully programmable timestamp on tx or rx, timestamp on gpio - 64-bit timer comparator event generation (gpio or irq) comprehensive power management features - 3 power-down levels - wake on link status change (energy detect) - magic packet wakeup, wake on lan (wol), wake on broadcast, wake on perfect da - wakeup indicator event signal - link status change power and i/o - integrated power-on reset circuit - latch-up performance exceeds 150ma per eia/jesd78, class ii - jedec class 3a esd performance - single 3.3v power supply (integrated 1.2v regulator) additional features - multifunction gpios - general purpose timer - optional eeprom interface - ability to use low cost 25mhz crystal for reduced bom packaging - pb-free rohs compliant 64-pin qfn or 64-pin tqfp- ep available in commercial, industrial, and extended industrial* temp. ranges *extended temp. (105oc) is supported only in the 64-qfn with an external voltage regulator (internal regulator must be disabled) and 2.5v (typ) ethernet magnetics. lan9250 10/100 industrial ethernet controller & phy downloaded from: http:///
lan9250 ds00001913a-page 2 ? 2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current documentation to obtain the most up-to-date version of this document ation, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 3 lan9250 1.0 preface ................................................................................................................... ......................................................................... 4 2.0 general description ........................................................................................................................................................................ 8 3.0 pin descriptions and configuration ........................................................................................ ....................................................... 10 4.0 power connections ......................................................................................................... .............................................................. 26 5.0 register map ................................................................................................................................................................................. 29 6.0 clocks, resets, and power management ...................................................................................... ............................................... 37 7.0 configuration straps ...................................................................................................... ............................................................... 54 8.0 system interrupts ......................................................................................................... ................................................................. 62 9.0 host bus interface ........................................................................................................................................................................ 74 10.0 spi/sqi slave ............................................................................................................ ............................................................... 121 11.0 host mac .................................................................................................................................................................................. 139 12.0 ethernet phy ............................................................................................................. ............................................................... 210 13.0 i2c master eeprom controller ............................................................................................................................................... 282 14.0 ieee 1588 ................................................................................................................................................................................. 298 15.0 general purpose timer & free-running clock ............................................................................... ......................................... 380 16.0 gpio/led controller ................................................................................................................................................................ 384 17.0 miscellaneous ........................................................................................................................................................................... 392 18.0 jtag ......................................................................................................................................................................................... 397 19.0 operational charac teristics .............................................................................................. ......................................................... 399 20.0 package outlines ......................................................................................................... ............................................................. 414 21.0 revision history ........................................................................................................................................................................ 417 downloaded from: http:///
lan9250 ds00001913a-page 4 ? 2015 microchip technology inc. 1.0 preface 1.1 general terms table 1-1: general terms term description 10base-t 10 mbps ethernet, ieee 802.3 compliant 100base-tx 100 mbps fast ethernet, ieee802.3u compliant adc analog-to-digital converter alr address logic resolution an auto-negotiation blw baseline wander bm buffer manager - part of the switch fabric bpdu bridge protocol data unit - messages which carry the spanning tree protocol informa- tion byte 8 bits csma/cd carrier sense multiple access/collision detect csr control and status registers ctr counter da destination address dword 32 bits epc eeprom controller fcs frame check sequence - the extra checksum characters added to the end of an ethernet frame, used for error detection and correction. fifo first in first out buffer fsm finite state machine gpio general purpose i/o host external system (includes proce ssor, application software, etc.) igmp internet group management protocol inbound refers to data input to the device from the host level-triggered sticky bit this type of status bit is set whenever the c ondition that it represents is asserted. the bit remains set until the condition is no longer true and the status bit is cleared by writ- ing a zero. lsb least significant bit lsb least significant byte lvds low voltage differential signaling mdi medium dependent interface mdix media independent interf ace with crossover mii media independent interface miim media independent interface management mil mac interface layer mld multicast listening discovery mlt-3 multi-level transmission encoding (3-levels). a tri-level encoding method where a change in the logic level represents a code bi t 1 and the logic output remaining at the same level represent s a code bit 0. msb most significant bit msb most significant byte downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 5 lan9250 nrzi non return to zero inverted. this encoding method inverts the signal for a 1 and leaves the signal unchanged for a 0 n/a not applicable nc no connect oui organizationally unique identifier outbound refers to data output fr om the device to the host piso parallel in serial out pll phase locked loop ptp precision time protocol reserved refers to a reserved bit field or address. unless otherwise noted, reserved bits must always be zero for write operations. unle ss otherwise noted, va lues are not guaran- teed when reading reserved bits. unless other wise noted, do not read or write to reserved addresses. rtc real-time clock sa source address sfd start of frame delimiter - the 8-bit value indicating the end of the preamble of an ethernet frame. sipo serial in parallel out smi serial management interface sqe signal quality error (also known as heartbeat) ssd start of stream delimiter udp user datagram protocol - a connectionl ess protocol run on top of ip networks uuid universally unique identifier word 16 bits table 1-1: general terms (continued) term description downloaded from: http:///
lan9250 ds00001913a-page 6 ? 2015 microchip technology inc. 1.2 buffer types table 1-2: buffer types buffer type description is schmitt-triggered input vis variable voltage schmitt-triggered input vo8 variable voltage output with 8 ma sink and 8 ma source vod8 variable voltage open-drain output with 8 ma sink vo12 variable voltage output with 12 ma sink and 12 ma source vod12 variable voltage open-drain output with 12 ma sink vos12 variable voltage open-sour ce output with 12 ma source vo16 variable voltage output with 16 ma sink and 16 ma source pu 50 a (typical) internal pull-up. unless other wise noted in the pin description, internal pull- ups are always enabled. internal pull-up resistors prevent unconnected inputs from floating. do not rely on in ternal resistors to drive signals external to the device. when connected to a load that must be pulled high, an external resistor must be added. pd 50 a (typical) internal pull-down. unless ot herwise noted in the pin description, internal pull-downs are always enabled. internal pull-down resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bidirectional iclk crystal oscillator input pin oclk crystal oscillator output pin ilvpecl low voltage pecl input pin olvpecl low voltage pecl output pin p power pin downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 7 lan9250 1.3 register nomenclature table 1-3: register nomenclature register bit type notation register bit description r read: a register or bit with this attribute can be read. w read: a register or bit with this attribute can be written. ro read only: read only. writes have no effect. wo write only: if a register or bit is write-on ly, reads will return unspecified data. wc write one to clear: writing a one clears the value. writing a zero has no effect wac write anything to clear: writing anything clears the value. rc read to clear: contents is cleared after the read. writes have no effect. ll latch low: clear on read of register. lh latch high: clear on read of register. sc self-clearing: contents are self-cleared after the being set. writes of zero have no effect. contents can be read. ss self-setting: contents are self-setting after bei ng cleared. writes of one have no effect. contents can be read. ro/lh read only, latch high: bits with this attribute will stay high until the bit is read. after it is read, the bit will either remain high if th e high condition remains, or will go low if the high condition has been removed. if the bit has not been read, the bit will remain high regardless of a change to the high condition. this mode is used in some ethernet phy registers. nasr not affected by software reset. the state of nasr bits do not change on assertion of a software reset. reserved reserved field: reserved fields must be written with zeros to ensure future compati- bility. the value of reserved bits is not guaranteed on a read. downloaded from: http:///
lan9250 ds00001913a-page 8 ? 2015 microchip technology inc. 2.0 general description the lan9250 is a full-featured, sing le-chip 10/100 ethernet controller desig ned for embedded applications where per- formance, flexibility, ease of integration and system cost control are required. the la n9250 has been specifically designed to provide high performance and throughput for 16-bit applications. the lan9250 complies with the ieee 802.3 (full/half -duplex 10base-t and 100base-tx) ethe rnet protocol, ieee 802.3az energy efficient ethernet (eee) (100mbps only), and the ieee 1588v2 pr ecision time protocol. 100base-fx is supported via an external fiber trans- ceiver. the lan9250 includes an integrated ethernet mac and ph y with a high-performance sram-like slave interface. the integrated checksum offload engines enable the automatic generation of the 16-bit checksum for received and trans- mitted ethernet frames, offloading the ta sk from the cpu. the lan9250 also includes large transmit and receive data fifos to accommodate high latency applications. in addition , the lan9250 memory buffer architecture allows highly efficient use of memory resources by optimizing packet granularity. the lan9250 also supports features which reduce or elimin ate packet loss. the internal 16-kbyte sram can hold over 200 received packets. if the receive fifo gets too full, the lan9250 can automatically generate flow control packets to the remote node, or assert back-pressure on t he remote node by generating network collisions. two user selectable host bus interface options are available: indexed register access this implementation provides three index/data regist er banks, each with independent byte/word to dword conversion. internal registers are access ed by first writing one of the three index registers, followed by reading or writing the corresponding data regist er. three index/data register banks support up to 3 independent driver threads without access conflicts. each thread can write its assigned index register without the issue of another thread overwriting it. two 16-bit cycles or four 8-bit cycles are required within the same 32-bit index/data register - however, these access can be interleav ed. direct (non-indexed) read and write accesses are supported to the packet data fifos. the direct fifo access provides independent byte/word to dw ord conversion, supporting interleaved accesses with the index/dat a registers. direct fifo access also supports burst reading of the data fifo. multiplexed address/data bus this implementation provides a multip lexed address and data bus with both single phase and dual phase address support. the address is loaded with an address strobe fo llowed by data access using a read or write strobe. two back to back 16-bit data cycles or 4 back to back 8-bit data cycles are required within the same 32-bit dword. these accesses must be sequential without any interleaved accesses to other regist ers. burst read and write accesses are supported to the packet data and status fifo s by performing one address cycle followed by multiple read or write data cycles. the hbi supports 8/16-bit operation with big, little, and mixed endian operations . four separate fi fo mechanisms (tx/ rx data fifos, tx/rx status fifos) interface the hbi to the host mac and facilitate the transferring of packet data and status information between the host cpu and the device. a configurable host interrupt pin allows the device to inform the host cpu of any internal interrupts. an spi / quad spi slave controller provides a low pin count synchronous slave interface that facilitates communication between the device and a host system. the spi / quad spi slave allows access to the system csrs, internal fifos and memories. it supports single and multiple register read and write commands with in crementing, decrementing and static addressing. single, dual and quad bit lanes are supported with a clock rate of up to 80 mhz. the lan9250 contains an i 2 c master eeprom controller for connection to an optional eeprom. this allows for the storage and retrieval of static data. the internal eeprom l oader can be optionally configured to automatically load stored configuration settings from the eeprom into the device at reset. the lan9250 supports numerous power management and wakeup features. the lan9250 can be placed in a reduced power mode and can be programmed to issue an external wake signal (pme) via several methods, including magic packet, wake on lan, wake on broadcast, wake on perfect da, and link status change. this signal is ideal for triggering system power-up using remote ethernet wakeup even ts. the device can be removed from the low power state via a host processor command or one of the wake events. the lan9250 can be configured to operate via a single 3.3v supply utilizing an integrated 3. 3v to 1.2v linear regulator. the linear regulator may be optionally disabled, allowing usa ge of a high efficiency external regulator for lower system power dissipation. the lan9250 is available in commercial, industr ial, and extended industrial temperature ranges. figure 2-1 provides an internal block diagram of the lan9250. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 9 lan9250 figure 2-1: internal block diagram lan9250 gpio/led controller to optional gpios/leds system interrupt controller irq gp timer free-run clk system clocks/ reset/pme controller external 25mhz crystal ieee 1588v2 clock/events 10/100 phy w/fiber w/802.3az registers ethernet register access mux spi slave controller i 2 c eeprom eeprom loader pin mux configuration to host bus, spi, i2c tx/rx fifos 10/100 mac w/ 802.3az, wol & 1588v2 registers host bus interface downloaded from: http:///
lan9250 ds00001913a-page 10 ? 2015 microchip technology inc. 3.0 pin descriptions and configuration 3.1 64-qfn pin assignments figure 3-1: 64-qfn pin assignments (top view) note: when a # is used at the end of the signal name, it indica tes that the signal is active low. for example, rst# indicates that the reset signal is active low. the buffer type for each signal is indicated in the b uffer type column of the pin description tables in sec- tion 3.3, "pin descriptions" . a description of the buffer types is provided in section 1.2, "buffer types" . note: exposed pad (vss ) on bottom of package must be connected to ground with a via field. (connect exposed pad to ground with a via field) vss lan9250 64-qfn (top view) 56 7 8 9 1011 12 2122 23 24 25 26 27 28 4443 42 41 40 39 38 37 6059 58 57 56 55 54 53 fxlosen reg_en fxsda/fxlosa/fxsdena reserved rst# d2/ad2/sio2 d1/ad1/so/sio1 vddio led1/gpio1/tdi/mngt1 led2/gpio2/e2psize eescl/tck vddcr d6/ad6 d3/ad3/sio3 rbias vdd12tx1 vdd33txrx1 vdd33bias rxpa cs a1/alelo d11/ad11 d12/ad12 vddio d9/ad9/sck txna eesda/tms txpa a2/alehi rxna vddcr irq 5251 6261 34 1314 1920 2930 3635 4645 d10/ad10 a3/mngt2 a4/mngt3 wr/enb vddcr vdd33 oscvss oscvdd12 vdd12tx2 reserved reserved reserved testmoded8/ad8 d7/ad7 vddio 12 osco osci 16 15 d13/ad13 d14/ad14 1718 d0/ad0/si/sio0 pme 32 vddio rd/rd_wr 31 3433 a0/d15/ad15 fifosel 48 vddio 47 led0/gpio0/tdo/mngt0 5049 d5/ad5/scs#d4/ad4 64 reserved vdd33txrx2 63 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 11 lan9250 table 3-1 details the 64-qfn package pin assignments in table format. as shown, select pin functions may change based on the devices mode of operati on. for modes where a specific pin has no function, the table cell will be marked with -. table 3-1: 64-qfn package pin assignments pin number hbi indexed mode pin name hbi multiplexed mode pin name spi mode pin name 1 osci 2 osco 3 oscvdd12 4 oscvss 5 vdd33 6 vddcr 7 reg_en 8 fxlosen 9 fxsda/fxlosa/fxsdena 10 reserved 11 rst# 12 d2 ad2 sio2 13 d1 ad1 so/sio1 14 vddio 15 d14 ad14 - 16 d13 ad13 - 17 d0 ad0 si/sio0 18 pme 19 d9 ad9 sck 20 vddio 21 d12 ad12 - 22 d11 ad11 - 23 d10 ad10 - 24 vddcr 25 a1 alelo - 26 a3 mngt2 - 27 a4 mngt3 - 28 cs - 29 a2 alehi - 30 wr/enb - 31 rd/rd_wr - 32 vddio downloaded from: http:///
lan9250 ds00001913a-page 12 ? 2015 microchip technology inc. 33 a0/d15 ad15 - 34 fifosel - 35 d3 ad3 sio3 36 d6 ad6 - 37 vddio 38 vddcr 39 d7 ad7 - 40 d8 ad8 - 41 testmode 42 eesda/tms 43 eescl/tck 44 irq 45 led2/gpio2/e2psize 46 led1/gpio1/tdi/mngt1 47 vddio 48 led0/gpio0/tdo/mngt0 49 d4 ad4 - 50 d5 ad5 scs# 51 vdd33txrx1 52 txna 53 txpa 54 rxna 55 rxpa 56 vdd12tx1 57 rbias 58 vdd33bias 59 vdd12tx2 60 reserved 61 reserved 62 reserved 63 reserved 64 vdd33txrx2 exposed pad vss table 3-1: 64-qfn package pin assignments (continued) pin number hbi indexed mode pin name hbi multiplexed mode pin name spi mode pin name downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 13 lan9250 3.2 64-tqfp-ep pin assignments figure 3-2: 64-tqfp-ep pin assignments (top view) note: exposed pad (vss ) on bottom of package must be connected to ground with a via field. (connect exposed pad to ground with a via field) vss lan9250 64-tqfp-ep (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 fxlosen reg_en fxsda/fxlosa/fxsdena reserved rst# d2/ad2/sio2 d1/ad1/so/sio1 vddio vddcr vdd33 oscvss oscvdd12 osco osci d13/ad13 d14/ad14 csa1/alelo d11/ad11 d12/ad12 vddio d9/ad9/sck a2/alehi vddcr d10/ad10 a3/mngt2 a4/mngt3 wr/enb d0/ad0/si/sio0 pme vddio rd/rd_wr led1/gpio1/tdi/mngt1 led2/gpio2/e2psize eescl/tck vddcr d6/ad6 d3/ad3/sio3 eesda/tms irqtestmode d8/ad8 d7/ad7 vddio a0/d15/ad15 fifosel vddio led0/gpio0/tdo/mngt0 rbias vdd12tx1 vdd33txrx1 vdd33bias rxpa txna txpa rxna vdd12tx2 reserved reserved reserved d5/ad5/scs# d4/ad4 reserved vdd33txrx2 downloaded from: http:///
lan9250 ds00001913a-page 14 ? 2015 microchip technology inc. table 3-2 details the 64-tqfp-ep package pin assignments in table format. as shown, select pin functions may change based on the devices mode of operati on. for modes where a specific pin has no function, the table cell will be marked with -. note: when a # is used at the end of the signal name, it indica tes that the signal is active low. for example, rst# indicates that the reset signal is active low. the buffer type for each signal is indicated in the b uffer type column of the pin description tables in sec- tion 3.3, "pin descriptions" . a description of the buffer types is provided in section 1.2, "buffer types" . table 3-2: 64-tqfp-ep package pin assignments pin number hbi indexed mode pin name hbi multiplexed mode pin name spi mode pin name 1 osci 2 osco 3 oscvdd12 4 oscvss 5 vdd33 6 vddcr 7 reg_en 8 fxlosen 9 fxsda/fxlosa/fxsdena 10 reserved 11 rst# 12 d2 ad2 sio2 13 d1 ad1 so/sio1 14 vddio 15 d14 ad14 - 16 d13 ad13 - 17 d0 ad0 si/sio0 18 pme 19 d9 ad9 sck 20 vddio 21 d12 ad12 - 22 d11 ad11 - 23 d10 ad10 - 24 vddcr 25 a1 alelo - 26 a3 mngt2 - 27 a4 mngt3 - 28 cs - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 15 lan9250 29 a2 alehi - 30 wr/enb - 31 rd/rd_wr - 32 vddio 33 a0/d15 ad15 - 34 fifosel - 35 d3 ad3 sio3 36 d6 ad6 - 37 vddio 38 vddcr 39 d7 ad7 - 40 d8 ad8 - 41 testmode 42 eesda/tms 43 eescl/tck 44 irq 45 led2/gpio2/e2psize 46 led1/gpio1/tdi/mngt1 47 vddio 48 led0/gpio0/tdo/mngt0 49 d4 ad4 - 50 d5 ad5 scs# 51 vdd33txrx1 52 txna 53 txpa 54 rxna 55 rxpa 56 vdd12tx1 57 rbias 58 vdd33bias 59 vdd12tx2 60 reserved 61 reserved 62 reserved 63 reserved table 3-2: 64-tqfp-ep package pin assignments (continued) pin number hbi indexed mode pin name hbi multiplexed mode pin name spi mode pin name downloaded from: http:///
lan9250 ds00001913a-page 16 ? 2015 microchip technology inc. 64 vdd33txrx2 exposed pad vss table 3-2: 64-tqfp-ep package pin assignments (continued) pin number hbi indexed mode pin name hbi multiplexed mode pin name spi mode pin name downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 17 lan9250 3.3 pin descriptions this section contains descriptions of the various lan9250 pins. the pin descriptions have been broken into functional groups as follows: lan pin descriptions host bus pin descriptions spi/sqi pin descriptions eeprom pin descriptions gpio, led & configuration strap pin descriptions miscellaneous pin descriptions jtag pin descriptions core and i/o power pin descriptions table 3-3: lan pin descriptions num pins name symbol buffer type description 1 tp tx/rx posi- tive channel 1 txpa aio twisted pair transmit/receive positive channel 1. see note 1 fx tx positive olvpecl fiber transmit positive. 1 tp tx/rx nega- tive channel 1 txna aio twisted pair transmit/receive negative channel 1. see note 1 . fx tx negative olvpecl fiber transmit negative. 1 tp tx/rx posi- tive channel 2 rxpa aio twisted pair transmit/receive positive channel 2. see note 1 . fx rx positive ai fiber receive positive. 1 tp tx/rx nega- tive channel 2 rxna aio twisted pair transmit/receive negative channel 2. see note 1 . fx rx negative ai fiber receive negative. downloaded from: http:///
lan9250 ds00001913a-page 18 ? 2015 microchip technology inc. 1 fx signal detect (sd) fxsda ilvpecl fiber signal detect. when fx-los mode is not selected, this pin functions as the signal detect input from the external transceiver. a level above 2 v (typ.) indicates valid signal. when fx-los mode is selected, the input buffer is disabled. fx loss of signal (los) fxlosa is (pu) fiber loss of signal. when fx-los mode is selected (via fx_los_strap_1 ), this pin functions as the loss of signal input from the external trans- ceiver. a high indicates los while a low indicates valid signal. when fx-los mode is not selected, the input buffer and pull-up are disabled. fx-sd enable strap fxsdena ai fx-sd enable. when fx-los mode is not selected, this strap input selects between fx-sd and copper twisted pair mode. a level above 1 v (typ.) selects fx-sd. when fx-los mode is selected, the input buffer is disabled. see note 2 . 1 bias reference rbias ai used for internal bias circuits. connect to an exter- nal 12.1 k ? , 1% resistor to ground. refer to the device reference schematic for connec- tion information. note: the nominal voltage is 1.2 v and the resistor will dissipate approximately 1 mw of power. 1 fx-los enable strap fxlosen ai fx-los enable. this strap input selects between fx-los and fx-sd / copper twisted pair mode. a level below 1 v (typ.) selects fx-sd / copper twisted pair for the port, further determined by fxs- dena . a level of 1.5 v (typ.) or above selects fx-los for the port. see note 2 . 1 +3.3 v analog power supply vdd33txrx1 p see note 3 . 1 +3.3 v analog power supply vdd33txrx2 p see note 3 . 1 +3.3 v master bias power supply vdd33bias p see note 3 . table 3-3: lan pin descriptions (continued) num pins name symbol buffer type description downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 19 lan9250 note 1: in copper mode, either channel 1 or 2 may function as the transmit pair while the other channel functions as the receive pair. the pin name symbols for the twisted pair pins apply to a normal connection. if hp auto- mdix is enabled and a reverse connection is detected or manually selected, the rx and tx pins will be swapped internally. note 2: configuration strap pins are ident ified by an underlined symbol name . configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 54 for more in formation. note 3: refer to section 4.0, "power connections," on page 26 , the device reference schematics, and the device lancheck schematic checklist for additional connection information. 1 transmitter +1.2 v power supply vdd12tx1 p this pin is supplied from either an external 1.2 v supply or from the devices internal regulator via the pcb. this pin must be tied to the vdd12tx2 pin for proper operation. see note 3 . 1 transmitter +1.2 v power supply vdd12tx2 p this pin is supplied from either an external 1.2 v supply or from the devices internal regulator via the pcb. this pin must be tied to the vdd12tx1 pin for proper operation. see note 3 . table 3-4: host bus pin descriptions num pins name symbol buffer type description 1 read rd vis this pin is the host bus read strobe. normally active low, the polarity can be changed via the hbi_rd_rdwr_polarity_strap . read or write rd_wr vis this pin is the host bus direction control. used in conjunction with the enb pin, it indicates a read or write operation. the normal polarity is read when 1, write when 0 (r/ nw) but can be changed via the hbi_rd_rdwr_polar- ity_strap . 1 write wr vis this pin is the host bus write strobe. normally active low, the polarity can be changed via the hbi_wr_en_polarity_strap . enable enb vis this pin is the host bus data enable strobe. used in conjunction with the rd_wr pin it indicates the data phase of the operation. normally active low, the polarity can be changed via the hbi_wr_en_polarity_strap . table 3-3: lan pin descriptions (continued) num pins name symbol buffer type description downloaded from: http:///
lan9250 ds00001913a-page 20 ? 2015 microchip technology inc. 1 chip select cs vis this pin is the host bus chip select and indicates that the device is select ed for the current transfer. normally active low, the polarity can be changed via the hbi_cs_polar ity_strap . 1 fifo select fifosel vis this input directly selects the host mac tx and rx data fifos for non-multiplexed address mode. 5a d d r e s s a[4:0] vis these pins provide the address for non-multiplexed address mode. in 16-bit data mode, bit 0 is not used. 16 data d[15:0] vis/vo8 these pins are the host bus data bus for non-multi- plexed address mode. in 8-bit data mode, bits 15-8 are not used and their input and output drivers are disabled. address & data ad[15:0] vis/vo8 these pins are the host bus address / data bus for multiplexed address mode. bits 15-8 provide the upper byte of address for sin- gle phase multiplexed address mode. bits 7-0 provide the lower byte of address for single phase multiplexed address mode and both bytes of address for dual phase multiplexed address mode. in 8-bit data dual phase multiplexed address mode, bits 15-8 are not used and their input and output drivers are disabled. 1 address latch enable high alehi vis this pin indicates the address phase for multiplexed address modes. it is used to load the higher address byte in dual phase multiplexed address mode. normally active low (address saved on rising edge), the polarity can be changed via the hbi_ale_polari- ty_strap . 1 address latch enable low alelo vis this pin indicates the address phase for multiplexed address modes. it is used to load both address bytes in single phase multiplexed address mode and the lower address byte in dual phase multi- plexed address mode. normally active low (address saved on rising edge), the polarity can be changed via the hbi_ale_polari- ty_strap . table 3-4: host bus pin descriptions (continued) num pins name symbol buffer type description downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 21 lan9250 note 4: although this pin is an output for spi instructions, it includes a pull-up since it is also sio bit 1. table 3-5: spi/sqi pin descriptions num pins name symbol buffer type description 1 spi/sqi slave chip select scs# vis (pu) this pin is the spi/sqi slave chip select input. when low, the spi/sqi slave is selected for spi/sqi transfers. when high, the spi/sqi serial data out- put(s) is(are) 3-stated. 1 spi/sqi slave serial clock sck vis (pu) this pin is the spi/sqi slave serial clock input. 4 spi/sqi slave serial data input/output sio[3:0] vis/vo8 (pu) these pins are the spi/sqi slave data input and output for multiple bit i/o. spi slave serial data input si vis (pu) this pin is the spi slave serial data input. si is shared with the sio0 pin. spi slave serial data output so vo8 (pu) note 4 this pin is the spi slave serial data output. so is shared with the sio1 pin. table 3-6: eeprom pin descriptions num pins name symbol buffer type description 1 eeprom i 2 c serial data input/output eesda vis/vod8 when the device is accessing an external eeprom this pin is the i 2 c serial data input/open-drain out- put. note: this pin must be pulled-up by an exter- nal resistor at all times. 1 eeprom i 2 c serial clock eescl vis/vod8 when the device is accessing an external eeprom this pin is the i 2 c clock input/open-drain output. note: this pin must be pulled-up by an exter- nal resistor at all times. downloaded from: http:///
lan9250 ds00001913a-page 22 ? 2015 microchip technology inc. table 3-7: gpio, led & configuration strap pin descriptions num pins name symbol buffer type description 1 led 2 led2 vo12/ vod12/ vos12 this pin is configured to operate as an led when the led 2 enable bit of the led configuration reg- ister (led_cfg) is set. the buffer type depends on the setting of the led function 2-0 (led_fun[2:0]) field in the led configuration register (led_cfg) and is configured to be either a push-pull or open- drain/open-source output. when selected as an open-drain/open-source output, the polarity of this pin depends upon the e2psize strap value sam- pled at reset. note: refer to section 16.3, "led operation," on page 385 to additional information. general purpose i/o 2 gpio2 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio when the led 2 enable bit of the led configuration reg- ister (led_cfg) is clear. the pin is fully program- mable as either a push-pull output, an open-drain output or a schmitt-triggered input by writing the general purpose i/o configuration register (gpi- o_cfg) and the general purpose i/o data & direc- tion register (gpio_data_dir) . eeprom size configuration strap e2psize vis (pu) this strap configures the value of the eeprom size hard-strap. see note 5 . a low selects 1k bits (128 x 8) through 16k bits (2k x 8). a high selects 32k bits (4k x 8) through 512k bits (64k x 8). 1 led 1 led1 vo12/ vod12/ vos12 this pin is configured to operate as an led when the led 1 enable bit of the led configuration reg- ister (led_cfg) is set. the buffer type depends on the setting of the led function 2-0 (led_fun[2:0]) field in the led configuration register (led_cfg) and is configured to be either a push-pull or open- drain/open-source output. when selected as an open-drain/open-source output, the polarity of this pin depends upon the mngt1 strap value sampled at reset. note: refer to section 16.3, "led operation," on page 385 to additional information. general purpose i/o 1 gpio1 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio when the led 1 enable bit of the led configuration reg- ister (led_cfg) is clear. the pin is fully program- mable as either a push-pull output, an open-drain output or a schmitt-triggered input by writing the general purpose i/o configuration register (gpi- o_cfg) and the general purpose i/o data & direc- tion register (gpio_data_dir) . host interface configuration strap 1 mngt1 vis (pu) this strap, along with mngt0 , mngt2 , and mngt3 configures the host interface mode. see note 5 . see table 7-3, hbi strap mapping, on page 61 for the host interface strap settings. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 23 lan9250 note 5: configuration strap pins are ident ified by an underlined symbol name . configuration strap values are latched on power-on reset or rst# de-assertion. refer to section 7.0, "configuration straps," on page 54 for more in formation. 1 led 0 led0 vo12/ vod12/ vos12 this pin is configured to operate as an led when the led 0 enable bit of the led configuration reg- ister (led_cfg) is set. the buffer type depends on the setting of the led function 2-0 (led_fun[2:0]) field in the led configuration register (led_cfg) and is configured to be either a push-pull or open- drain/open-source output. when selected as an open-drain/open-source output, the polarity of this pin depends upon the mngt0 strap value sampled at reset. note: refer to section 16.3, "led operation," on page 385 to additional information. general purpose i/o 0 gpio0 vis/vo12/ vod12 (pu) this pin is configured to operate as a gpio when the led 0 enable bit of the led configuration reg- ister (led_cfg) is clear. the pin is fully program- mable as either a push-pull output, an open-drain output or a schmitt-triggered input by writing the general purpose i/o configuration register (gpi- o_cfg) and the general purpose i/o data & direc- tion register (gpio_data_dir) . host interface configuration strap 0 mngt0 vis (pu) this strap, along with mngt1 , mngt2 , and mngt3 configures the host mode. see note 5 . see table 7-3, hbi strap mapping, on page 61 for the host interface strap settings. 1 host interface configuration strap 3 mngt3 vis (pu) this strap, along with mngt0 , mngt1 , and mngt2 configures the host mode. see note 5 . see table 7-3, hbi strap mapping, on page 61 for the host interface strap settings. 1 host interface configuration strap 2 mngt2 vis (pu) this strap, along with mngt0 , mngt1 , and mngt3 configures the host mode. see note 5 . see table 7-3, hbi strap mapping, on page 61 for the host interface strap settings. table 3-7: gpio, led & configuration strap pin descriptions (continued) num pins name symbol buffer type description downloaded from: http:///
lan9250 ds00001913a-page 24 ? 2015 microchip technology inc. table 3-8: miscellaneous pin descriptions num pins name symbol buffer type description 1 power management event output pme vo8/vod8 when programmed accordingly this signal is asserted upon detection of a wakeup event. the polarity and buffer type of this signal is programma- ble via the pme enable (pme_en) bit of the power management control register (pmt_ctrl) . refer to section 6.0, "clocks, resets, and power management," on page 37 for additional information on the power management features. 1 interrupt output irq vo8/vod8 interrupt request output. the polarity, source and buffer type of this signal is programmable via the interrupt configuration register (irq_cfg) . for more information, refer to section 8.0, "system interrupts," on page 62 . 1 system reset input rst# vis (pu) as an input, this active low signal allows external hardware to reset the device. the device also con- tains an internal power-on reset circuit. thus this signal may be left unconnected if an external hard- ware reset is not needed. when used this signal must adhere to the reset timing requirements as detailed in the section 19.0, "operational character- istics," on page 399 . 1 regulator enable reg_en ai when tied to 3.3 v, the internal 1.2 v regulators are enabled. 1 test mode testmode vis (pd) this pin must be tied to vss for proper operation. 1 crystal input osci iclk external 25 mhz crystal input. this signal can also be driven by a single-ended clock oscillator. when this method is used, osco should be left uncon- nected. 1 crystal output osco oclk external 25 mhz crystal output. 1 crystal +1.2 v power supply oscvdd12 p supplied by the on-chip regulator unless configured for regulator off mode via reg_en . 1 crystal ground oscvss p crystal ground. 5 reserved reserved - this pin is reserved and must be left unconnected for proper operation. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 25 lan9250 note 6: refer to section 4.0, "power connections," on page 26 , the device reference schematic, and the device lancheck schematic checklist for additional connection information. table 3-9: jtag pin descriptions num pins name symbol buffer type description 1 jtag test mux select tms vis jtag test mode select 1 jtag test clock tck vis jtag test clock 1 jtag test data input tdi vis jtag data input 1 jtag test data output tdo vo12 jtag data output table 3-10: core and i/o power pin descriptions num pins name symbol buffer type description 1 regulator +3.3 v power supply vdd33 p +3.3 v power supply for internal regulators. see note 6 . note: +3.3 v must be supplied to this pin even if the internal regulators are disabled. 5 +1.8 v to +3.3 v variable i/o power vddio p +1.8 v to +3.3 v variable i/o power. see note 6 . 3 +1.2 v digital core power supply vddcr p supplied by the on-chip regulator unless configured for regulator off mode via reg_en . 1 f and 470 pf decoupling capacitors in parallel to ground should be used on pin 6. see note 6 . 1 pad ground vss p common ground. this exposed pad must be con- nected to the ground plane with a via array. downloaded from: http:///
lan9250 ds00001913a-page 26 ? 2015 microchip technology inc. 4.0 power connections figure 4-1 and figure 4-2 illustrate the device power connections for regulator enabled and disabled cases, respec- tively. refer to the device reference schematic and the de vice lancheck schematic check list for additional information. section 4.1 provides additional information on the devices internal voltage regulators. figure 4-1: power connecti ons - regulators enabled +1.8 v to +3.3 v vddcr core logic & phy digital vdd12tx2 ethernet phy analog 1.0 f 0.1 ? esr vdd33bias vdd33txrx1 vss vddcr pll vdd12tx1 vdd33txrx2 ethernet master bias io pads to phy1 magnetics note: bypass and bulk caps as needed for pcb vddio vdd33 +3.3 v +3.3 v 470 pf crystal oscillator vss (exposed pad) (or separate 2.5v) vddio vddio vddio vddio vddcr oscvdd12 oscvss +3.3 v (in) +1.2 v (out) internal 1.2 v core regulator enable +3.3 v (in) +1.2 v (out) internal 1.2 v oscillator regulator vss enable reg_en (pin 6) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 27 lan9250 figure 4-2: power connections - regulators disabled +1.8 v to +3.3 v vddcr core logic & phy digital vdd12tx2 ethernet phy analog vdd33bias vdd33txrx1 vss vddcr pll vdd12tx1 vdd33txrx2 ethernet master bias io pads to phy1 magnetics note: bypass and bulk caps as needed for pcb vddio vdd33 +3.3 v +3.3 v crystal oscillator vss (exposed pad) (or separate 2.5v) vddio vddio vddio vddio vddcr oscvdd12 oscvss +3.3 v (in) +1.2 v (out) internal 1.2 v core regulator enable +3.3 v (in) +1.2 v (out) internal 1.2 v oscillator regulator vss enable reg_en +1.2 v (pin 6) downloaded from: http:///
lan9250 ds00001913a-page 28 ? 2015 microchip technology inc. 4.1 internal voltage regulators the device contains two internal 1.2 v regulators: 1.2 v core regulator 1.2 v crystal oscillator regulator 4.1.1 1.2 v core regulator the core regulator supplies 1.2 v volts to the main core digital logic, the i/o pads, and the phys digital logic and can be used to supply the 1.2 v power to the phy analog sections (via an external connection). when the reg_en input pin is connected to 3.3 v, the core regulator is enabled and receives 3.3 v on the vdd33 pin. a 1.0 uf 0.1 ? esr capacitor must be connected to the vddcr pin associated with the regulator. when the reg_en input pin is connected to vss , the core regulator is disabled. however, 3.3 v must still be supplied to the vdd33 pin. the 1.2 v core voltage must then be externally input into the vddcr pins. 4.1.2 1.2 v crystal oscillator regulator the crystal oscillator regulator supplies 1.2 v volts to the crystal oscillator. when the reg_en input pin is connected to 3.3 v, the crystal oscillator regulator is enabled and receives 3.3 v on the vdd33 pin. an external capacitor is not required. when the reg_en input pin is connected to vss , the crystal oscillator regulator is disabled. however, 3.3 v must still be supplied to the vdd33 pin. the 1.2 v crystal oscillator volta ge must then be externally input into the oscvdd12 pin. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 29 lan9250 5.0 register map this chapter details the device regist er map and summarizes the various dire ctly addressable system control and sta- tus registers (csrs). detailed descriptions of the system cs rs are provided in the chapters corresponding to their function. additional indi rectly addressable registers are available in the vari ous sub-blocks of the device. these regis- ters are also detailed in their corresponding chapters. directly addressable registers section 11.10.1, "tx/rx fifos," on page 157 section 5.1, "system control an d status registers," on page 31 indirectly addressable registers section 11.15, "host mac control and status registers," on page 192 section 12.2.18, "phy registers," on page 230 figure 5-1 contains an overall base register memory map of t he device. this memory map is not drawn to scale, and should be used for general reference only. table 5-1 provides a summary of all directly addressable csrs and their corresponding addresses. note: register bit type definitions are provided in section 1.3, "register nomenclature," on page 7 . not all device registers are memory mapped or directly addressable. for details on the accessibility of the various device registers, refer the register sub- sections listed above. downloaded from: http:///
lan9250 ds00001913a-page 30 ? 2015 microchip technology inc. figure 5-1: register address map rx data fifo port & alias ports tx data fifo port & alias ports rx status fifo port rx status fifo peek tx status fifo port tx status fifo peek 000h 020h 040h 044h 048h 04ch 100h03ch 01ch 1588 registers 18ch host mac indirect access 0a4h 0a8h tx & rx data fifo configuration 080h068h 0ach host mac eee 0bch test 0e0h 0fch gpio 1e0h 1e8h 3ffh interrupts 054h 05ch eeprom 1b4h 1b8h host mac 0a0h gp timer and free run counter 09ch08ch led configuration 1bch host mac 0b0h note: not all registers are shown 1c0h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 31 lan9250 5.1 system control and status registers the system csrs are directly addressable memory mapped r egisters with a base address offset range of 050h to 1f8h. these registers are addressable by the host via the host bus interface (hbi) or spi/sqi . for more information on the various device modes and their corresponding address configurations, see section 2.0, "general description," on page 8 . table 5-1 lists the system csrs and their corresponding addresses in order. all system csrs are reset to their default value on the assertion of a chip-level reset. the system csrs can be divided into the following sub-categor ies. each of these sub-categories is located in the cor- responding chapter and contains the s ystem csr descriptions of the associated registers. the register descriptions are categorized as follows: section 6.2.3, "reset registers," on page 42 section 6.3.5, "power manag ement registers," on page 49 section 8.3, "interrupt registers," on page 65 section 11.14, "host mac & fifo interface registers," on page 176 section 16.4, "gpio/led registers," on page 386 section 13.5, "i2c master eeprom controller registers," on page 294 section 14.8, "1588 registers," on page 316 section 17.1, "miscellaneous system conf iguration & status registers," on page 392 note: unlisted registers are reserved for future use. table 5-1: system control and status registers address register name (symbol) 000h - 04ch tx/rx fifos 050h chip id and revision (id_rev) 054h interrupt configuration register (irq_cfg) 058h interrupt status register (int_sts) 05ch interrupt enable register (int_en) 064h byte order test re gister (byte_test) 068h fifo level interrupt register (fifo_int) 06ch receive configuration register (rx_cfg) 070h transmit configuration register (tx_cfg) 074h hardware configuration register (hw_cfg) 078h receive datapath control register (rx_dp_ctrl) 07ch rx fifo information register (rx_fifo_inf) 080h tx fifo information r egister (tx_fifo_inf) 084h power management control register (pmt_ctrl) 08ch general purpose timer config uration register (gpt_cfg) 090h general purpose timer count register (gpt_cnt) 09ch free running 25mhz counter register (free_run) 0a0h host mac rx dropped frames counter register (rx_drop) 0a4h host mac csr interface command register (mac_csr_cmd) 0a8h host mac csr interface data register (mac_csr_data) 0ach host mac automatic flow control configuration register (afc_cfg) 0b0h host mac rx lpi transitions r egister (hmac_rx_lpi_transition) 0b4h host mac rx lpi time register (hmac_rx_lpi_time) 0b8h host mac tx lpi transitions register (hmac_tx_lpi_transition) 0bch host mac tx lpi time register (hmac_tx_lpi_time) downloaded from: http:///
lan9250 ds00001913a-page 32 ? 2015 microchip technology inc. 1588 registers 100h 1588 command and control register (1588_cmd_ctl) 104h 1588 general configuration register (1588_general_config) 108h 1588 interrupt status register (1588_int_sts) 10ch 1588 interrupt enable register (1588_int_en) 110h 1588 clock seconds register (1588_clock_sec) 114h 1588 clock nanoseconds register (1588_clock_ns) 118h 1588 clock sub-nanoseconds register (1588_clock_subns) 11ch 1588 clock rate adjustment register (1588_clock_rate_adj) 120h 1588 clock temporary rate adjustment register (1588_clock_temp_rate_adj) 124h 1588 clock temporary rate duration register (1588_clock_temp_rate_duration) 128h 1588 clock step adjustment re gister (1588_clock_step_adj) 12ch 1588 clock target x seconds register (1588_clock_target_sec_x) x=a 130h 1588 clock target x nanoseconds register (1588_clock_target_ns_x) x=a 134h 1588 clock target x reload / add seconds re gister (1588_clock_target_reload_sec_x) x=a 138h 1588 clock target x reload / add nanose conds register (1588_clock_target_re- load_ns_x) x=a 13ch 1588 clock target x seconds register (1588_clock_target_sec_x) x=b 140h 1588 clock target x nanoseconds register (1588_clock_target_ns_x) x=b 144h 1588 clock target x reload / add seconds re gister (1588_clock_target_reload_sec_x) x=b 148h 1588 clock target x reload / add nanose conds register (1588_clock_target_re- load_ns_x) x=b 14ch 1588 user mac address high-word register (1588_user_mac_hi) 150h 1588 user mac address low-dwo rd register (1588_user_mac_lo) 154h 1588 bank port gpio select regi ster (1588_bank_port_gpio_sel) 158h 1588 port latency register (1588_latency) 158h 1588 port rx parsing configuration register (1588_rx_parse_config) 158h 1588 port tx parsing configuration register (1588_tx_parse_config) 15ch 1588 port asymmetry and peer delay register (1588_asym_peerdly) 15ch 1588 port rx timestamp configuration register (1588_rx_timestamp_config) 15ch 1588 port tx timestamp configuration register (1588_tx_timestamp_config) 15ch 1588 gpio capture configuration register (1588_gpio_cap_config) 160h 1588 port capture information register (1588_cap_info) 160h 1588 port rx timestamp insertion configur ation register (1588_rx_ts_insert_config) 164h 1588 port tx modification register (1588_tx_mod) 168h 1588 port rx filter configuratio n register (1588_rx_filter_config) 168h 1588 port tx modification register 2 (1588_tx_mod2) 16ch 1588 port rx ingress time seconds register (1588_rx_ingress_sec) 16ch 1588 port tx egress time second s register (1588_tx_egress_sec) 16ch 1588 gpio x rising edge clock seconds capture register (1588_gpio_re_clock_sec_cap_x) 170h 1588 port rx ingress time nanoseconds register (1588_rx_ingress_ns) 170h 1588 port tx egress time nanoseconds register (1588_tx_egress_ns) table 5-1: system control and st atus registers (continued) address register name (symbol) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 33 lan9250 170h 1588 gpio x rising edge clock nanoseconds capture register (1588_gpio_re_clock_ns_- cap_x) 174h 1588 port rx message header register (1588_rx_msg_header) 174h 1588 port tx message header register (1588_tx_msg_header) 178h 1588 port rx pdelay_req ingress time seconds register (1588_rx_pdreq_sec) 178h 1588 port tx delay_req egress time seconds register (1588_tx_dreq_sec) 178h 1588 gpio x falling edge clock seconds captur e register (1588_gpio_fe_clock_sec_cap_x) 17ch 1588 port rx pdelay_req ingress time nanoseconds register (1588_rx_pdreq_ns) 17ch 1588 port tx delay_req egress time nanoseconds register (1588_tx_dreq_ns) 17ch 1588 gpio x falling edge clock nanoseconds capture register (1588_gpio_fe_clock_ns_- cap_x) 180h 1588 port rx pdelay_req ingress correction field high register (1588_rx_pdreq_cf_hi) 180h 1588 tx one-step sync upper seconds register (1588_tx_one_step_sync_sec) 184h 1588 port rx pdelay_req ingress correction field low register (1588_rx_pdreq_cf_low) 188h 1588 port rx checksum dropped count re gister (1588_rx_ch ksum_dropped_cnt) 18ch 1588 port rx filtered count register (1588_rx_filtered_cnt) eeprom/led registers 1b4h eeprom command register (e2p_cmd) 1b8h eeprom data register (e2p_data) 1bch led configuration register (led_cfg) gpio registers 1e0h general purpose i/o configuration register (gpio_cfg) 1e4h general purpose i/o data & direction register (gpio_data_dir) 1e8h general purpose i/o interrupt status and enable register (gpio_int_sts_en) reset register 1f8h reset control register (reset_ctl) table 5-1: system control and st atus registers (continued) address register name (symbol) downloaded from: http:///
lan9250 ds00001913a-page 34 ? 2015 microchip technology inc. 5.2 special restrictions on back-to-back cycles 5.2.1 back-to-back write-read cycles it is important to note that there are sp ecific restrictions on the timing of back-to -back host write-read operations. these restrictions concern reading re gisters after any write cycle that may affect the register. in all cases there is a delay between writing to a register and the new value becoming available to be read. in other cases, there is a delay between writing to a register and the subseque nt side effect on other registers. in order to prevent the host from reading stale data after a write operation, minimum wait periods have been established. these periods are specified in ta b l e 5 - 2 . the host processor is required to wait t he specified period of time after writing to the indicated register before reading the resource specified in the table. no te that the required wait period is depen- dent upon the register being read after the write. performing dummy reads of the byte order test register (byte_test) register is a convenient way to guarantee that the minimum write-to-read ti ming restriction is met. ta b l e 5 - 2 shows the number of dummy reads that are required before reading the register in dicated. the number of byte_ test reads in this table is based on the minimum cycle timing of 45ns. for microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the tabl e. note that dummy reads of the byte_test register are not required as long as the minimum time period is met. note that depending on the host interface mode in use, th e basic host interface cycle may naturally provide sufficient time between writes and read. it is required of the system design and register access mechanisms to ensure the proper timing. for example, a wr ite and read to the same register may occur fa ster than a write and read to different registers. for 8 and 16-bit write cycles, the wait time for the back-to-back write-read operat ion applies only to the writing of the last byte or word of the register, which completes a single dword transfer. for indexed address mode hbi operation, the wait time for the back-to-ba ck write-read operation applies only to access to the internal registers and fifos. it does not apply to the host bus interface index registers or the host bus interface configuration register. table 5-2: read after write timing rules after writing... wait for this many nanoseconds... or perform this many reads of byte_test (assuming t cyc of 45ns) before reading... any register 45 1 the same register or any other register affected by the write host mac tx data fifo 135 3 tx fifo information register (tx_fifo_inf) interrupt configuration regis- ter (irq_cfg) 60 2 interrupt configuration regis- ter (irq_cfg) interrupt enable register (int_en) 90 2 interrupt configuration regis- ter (irq_cfg) 60 2 interrupt status register (int_sts) interrupt status register (int_sts) 180 4 interrupt configuration regis- ter (irq_cfg) 170 4 interrupt status register (int_sts) fifo level interrupt register (fifo_int) 90 2 interrupt configuration regis- ter (irq_cfg) 80 2 interrupt status register (int_sts) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 35 lan9250 5.2.2 back-to-back read cycles there are also restrictions on specific back-to-back host re ad operations. these restrictions concern reading specific registers after reading a resource that has side effects. in many cases there is a delay between reading the device, and the subsequent indication of the expected change in the control and status register values. in order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab- lished. these periods are specified in table 5-3 . the host processor is required to wait the specified period of time between read operations of specific combinations of res ources. the wait period is dependent upon the combination of registers being read. performing dummy reads of the byte order test register (byte_test) register is a convenient way to guarantee that the minimum wait time restriction is met. table 5-3 below also shows the number of dummy reads that are required for back-to-back read operations. the number of byte_test read s in this table is based on the minimum timing for t cyc receive configuration regis- ter (rx_cfg) 80 2 interrupt configuration regis- ter (irq_cfg) 60 2 interrupt status register (int_sts) 50 2 interrupt configuration regis- ter (irq_cfg) power management control register (pmt_ctrl) 165 4 power management control register (pmt_ctrl) 170 4 interrupt configuration regis- ter (irq_cfg) 160 4 interrupt status register (int_sts) general purpose timer con- figuration register (gpt_cfg) 55 2 general purpose timer con- figuration register (gpt_cfg) 170 4 general purpose timer count register (gpt_cnt) 1588 command and control register (1588_cmd_ctl) 70 2 interrupt configuration regis- ter (irq_cfg) 50 2 interrupt status register (int_sts) 50 2 1588 interrupt status register (1588_int_sts) 1588 interrupt status register (1588_int_sts) 60 2 interrupt configuration regis- ter (irq_cfg) 1588 interrupt enable regis- ter (1588_int_en) 60 2 interrupt configuration regis- ter (irq_cfg) general purpose i/o interrupt status and enable register (gpio_int_sts_en) 60 2 interrupt configuration regis- ter (irq_cfg) table 5-2: read after write timing rules (continued) after writing... wait for this many nanoseconds... or perform this many reads of byte_test (assuming t cyc of 45ns) before reading... downloaded from: http:///
lan9250 ds00001913a-page 36 ? 2015 microchip technology inc. (45ns). for microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. dummy reads of the byte_t est register are not required as long as the minimum time period is met. note that depending on the host interface mode in use, th e basic host interface cycle may naturally provide sufficient time between reads. it is required of the system design and register access mechanisms to ensure the proper timing. for example, multiple reads to the same register may occur faster than reads to different registers. for 8 and 16-bit r ead cycles, the wait time fo r the back-to-back read oper ation is required only after the reading of the last byte or word of the register, which completes a sing le dword transfer. there is no wait requirement between the byte or word accesses within the dword transfer. table 5-3: read after read timing rules after reading... wait for this many nanoseconds... or perform this many reads of byte_test (assuming t cyc of 45ns) before reading... host mac rx data fifo 135 3 rx fifo information regis- ter (rx_fifo_inf) host mac rx status fifo 135 3 rx fifo information regis- ter (rx_fifo_inf) host mac tx status fifo 135 3 tx fifo information register (tx_fifo_inf) host mac rx dropped frames counter register (rx_drop) 180 4 host mac rx dropped frames counter register (rx_drop) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 37 lan9250 6.0 clocks, resets, a nd power management 6.1 clocks the device provides generation of all sys tem clocks as required by the various sub-modules of the device. the clocking sub-system is comprised of the following: crystal oscillator phy pll 6.1.1 crystal oscillator the device requires a fixed-frequency 25 mhz clock source for use by the internal clock oscillator and pll. this is typ- ically provided by attaching a 25 mhz crystal to the osci and osco pins as specified in section 19.7, "clock circuit," on page 413 . optionally, this clock can be provided by driving the osci input pin with a single-ended 25 mhz clock source. if a single-ended source is sele cted, the clock input must run continuous ly for normal device operation. power savings modes allow for the oscillator or external clock input to be halted. the crystal oscillator can be disabled as describe in section 6.3.4, "chip level power management," on page 47 . for system level verificati on, the crystal oscillator output ca n be enabled onto the irq pin. see section 8.2.9, "clock output test mode," on page 65 . power for the crystal oscillator is provided by a dedicated regulator or separate input pin. see section 4.1.2, "1.2 v crys- tal oscillator regulator," on page 28 . 6.1.2 phy pll the phy module receives the 25 mhz reference clock and, in addition to its internal clock usage, outputs a main system clock that is used to de rive device sub-system clocks. the phy pll can be disabled as describe in section 6.3.4, "chip level power management," on page 47 . the phy pll will be disabled only when requested and if the phy port is in a power down mode. power for phy pll is provided by an external input pin, us ually sourced by the devices 1.2v core regulator. see section 4.0, "power connections," on page 26 . note: crystal specifications are provided in table 19-13, crystal specifications, on page 413 . downloaded from: http:///
lan9250 ds00001913a-page 38 ? 2015 microchip technology inc. 6.2 resets the device provides multiple hardware and software reset s ources, which allow varying levels of the device to be reset. all resets can be categorized into three reset types as described in the following sections: chip-level resets - power-on reset (por) - rst# pin reset multi-module resets - digital reset (digital_rst) single-module resets - phy reset - host mac sub-system reset - 1588 reset the device supports the use of configuratio n straps to allow automatic custom configurations of various device param- eters. these configurati on strap values are set upon de-assertion of all chip-level resets and can be used to easily set the default parameters of the chip at power-on or pin (rst#) reset. refer to section 6.3, "power management," on page 44 for detailed information on the usage of these straps. table 6-1 summarizes the effect of the various reset sources on the device. refer to the following sections for detailed information on each of these reset types. table 6-1: reset sources and affected device functionality module/ functionality por rst# pin digital reset 25 mhz oscillator ( 1 ) voltage regulators ( 2 ) host mac sub-system xxx phy xx phy common ( 3 ) voltage supervision ( 3 ) pll ( 3 ) 1588 clock / event gen. xxx 1588 timestamp unit 0 xxx 1588 timestamp unit 1 xxx 1588 timestamp unit 2 xxx spi/sqi slave xxx host bus interface xxx power management xxx device eeprom loader xxx i2c master xxx gpio/led controller xxx general purpose timer xxx free running counter xxx system csr xxx config. straps latched yes yes no( 4 ) eeprom loader run yes yes yes reload host mac addr. ( 5 )( 5 )( 5 ) tristate output pins ( 6 ) yes yes note 1: por is performed by the xtal voltage regulator, not at the system level 2: por is performed internal to the voltage regulators 3: por is performed internal to the phy 4: strap inputs are not re-latched, however soft-straps are retu rned to their previously latched pin defaults before they are potentially updated by the eeprom values. 5: part of eeprom loading 6: only those output pins that are used for straps downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 39 lan9250 6.2.1 chip-level resets a chip-level reset event activates all internal resets, effectiv ely resetting the entire device. a chip-level reset is initiate d by assertion of any of the following input events: power-on reset (por) rst# pin reset chip-level reset/configuration completion can be determined by first polling the byte order test register (byte_test) . the returned data will be invalid until the host interface resets are complete. once the returned data is the correct byte ordering value, the host interface resets have completed. the completion of the entire chip-level reset mu st be determined by polling the ready bit of the hardware configura- tion register (hw_cfg) or power management control register (pmt_ctrl) until it is set. when set, the ready bit indicates that the reset has completed and the device is ready to be accessed. with the exception of the hardware configuration register (hw_cfg) , power management control register (pmt_c- trl) , byte order test register (byte_test) , and reset control register (reset_ctl) , read access to any internal resources should not be done by s/w while the ready bit is cl eared. writes to any addre ss are invalid until the ready bit is set. a chip-level reset involves tuning of the variable output le vel pads, latching of configuration straps and generation of the master reset. configuration straps latching during por or rst# pin reset, the latches for the straps are open. following the release of por or rst# pin reset, the latches for the straps are closed. variable level i/o pad tuning following the release of the por or rst# pin resets, a 1 us pulse (active low), is sent into the vo tuning circuit. 2 us later, the output pins are enabled. the 2 us delay allows time for the variable output leve l pins to tune before enabling the outputs and also provides input hold time for strap pins that are s hared with output pins. master reset and clock generation reset following the enabling of the output pins, the rese t is synchronized to the main syst em clock to become the master reset. master reset is used to generate the lo cal resets and to reset the clocks generation. 6.2.1.1 power-on reset (por) a power-on reset occurs whenever power is initially applied to the device or if the power is removed and reapplied to the device. this event resets all circuitry within the dev ice. configuration straps are latched and eeprom loading is performed as a result of this reset. the por is used to tr igger the tuning of the variable level i/o pads as well as a chip-level reset. following valid voltage levels, a por reset typically takes approximately 21 ms, plus any additional time (91 us per byte) for data loaded from the eeprom. a full 64kb eeprom load would complete in approximately 6 seconds. rst# pin driven low table 6-1: reset sources and affected device functionality (continued) module/ functionality por rst# pin digital reset note 1: por is performed by the xtal voltage regulator, not at the system level 2: por is performed internal to the voltage regulators 3: por is performed internal to the phy 4: strap inputs are not re-latched, however soft-straps are retu rned to their previously latched pin defaults before they are potentially updated by the eeprom values. 5: part of eeprom loading 6: only those output pins that are used for straps downloaded from: http:///
lan9250 ds00001913a-page 40 ? 2015 microchip technology inc. 6.2.1.2 rst# pin reset driving the rst# input pin low initiates a chip-level reset. this ev ent resets all circuitry within the device. use of this reset input is optional, but when used, it must be driven for the period of time specified in section 19.6.3, "reset and configuration strap timing," on page 410 . configuration straps are latched, and eeprom loading is performed as a result of this reset. a rst# pin reset typically takes approximately 760 ? s plus any additional time (91 us per byte) for data loaded from the eeprom. a full 64kb eeprom load would complete in approximately 6 seconds. please refer to table 3-8, miscellaneous pin descriptions, on page 24 for a description of the rst# pin. 6.2.2 block-level resets the block level resets co ntain an assortment of reset regi ster bit inputs and generate resets for the various blocks. block level resets can affect one or multiple modules. 6.2.2.1 multi-module resets multi-module resets activate multiple internal resets, but do not reset the entire ch ip. configuration straps are not latched upon multi-module resets. a multi-module reset is initiated by assertion of the following: digital reset (digital_rst) multi-module reset/configuration completion can be determined by first polling the byte order test register (byte_test) . the returned data will be invalid until the host interface resets are complete. once the returned data is the correct byte ordering value, the ho st interface resets have completed. the completion of the entire chip-level reset mu st be determined by polling the ready bit of the hardware configura- tion register (hw_cfg) or power management control register (pmt_ctrl) until it is set. when set, the ready bit indicates that the reset has completed and the device is ready to be accessed. with the exception of the hardware configuration register (hw_cfg) , power management control register (pmt_c- trl) , byte order test register (byte_test) , and reset control register (reset_ctl) , read access to any internal resources should not be done by s/w while the ready bit is cleared. writes to any address are invalid until the ready bit is set. digital reset (digital_rst) a digital reset is performed by setting the digital_rst bit of the reset control register (reset_ctl) . a digital reset will reset all device sub-modules except the ethernet phy. eeprom loading is performed following this reset. config- uration straps are not latched as a result of a digital reset. however, soft straps are first returned to their previously latched pin values and register bits that default to strap values are reloaded. a digital reset typically takes approximately 760 ? s plus any additional time (91 us per byte) for data loaded from the eeprom. a full 64kb eeprom load would complete in approximately 6 seconds. 6.2.2.2 single-module resets a single-module reset will reset only the specified module. single-module resets do not latch the configuration straps or initiate the eeprom loader. a si ngle-module reset is initiated by assertio n of the following: phy reset host mac sub-system reset 1588 reset phy reset a phy reset is performed by setting the phy_rst bit of the reset control register (reset_ctl) or the soft reset bit in the phy basic control register (phy_basic_control) . upon completion of the phy reset, the phy_rst and soft reset bits are automatically cleared. no other modules of the device are affected by this reset. note: the rst# pin is pulled-high internally. if unused, this signal can be left unconnected. do not rely on internal pull-up resistors to drive signals external to the device. note: the digital reset does not reset register bits designated as nasr. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 41 lan9250 phy reset completion can be determined by polling the phy_rst bit in the reset control register (reset_ctl) or the soft reset bit in the phy basic control regist er (phy_basic_control) until it clears. under normal conditions, the phy_rst and soft reset bit will clear approximately 102 us after the phy reset occurrence. in addition to the methods above, the phy is automatically reset after returning from a phy power-down mode. this reset differs in that the phy power-down mode reset does not reload or reset any of the phy registers. refer to section 12.2.10, "phy power-down modes," on page 222 for additional information. refer to section 12.2.12, "resets," on page 224 for additional information on phy resets. host mac sub-system reset a host mac sub-system reset is performe d by setting the hmac_rst bit in the reset control register (reset_ctl) . in addition, the mac address of the host mac is reloaded from the eeprom, using the device eeprom loader. this will reset the host mac and fifos, including: mac address filtering wake-on-lan rx checksum offload tx checksum offload energy efficient ethernet control and counters fifos flow control logic the following registers and register fields will be reset: all registers described in section 11.14, "host mac & fifo interface registers," on page 176 note: the hbi register locks associated with these register are also reset. all registers described in section 11.15, "host mac control and status registers," on page 192 ? the eeprom controller busy (epc_busy) and configuration loaded (cfg_loaded) bits in the eeprom command register (e2p_cmd) (set and cleared respectively) note: the bits in the interrupt status register (int_sts) listed in section 8.2.4, "host mac interrupts" are not reset. note: host mac and fifo related bits in the hardware configuration register (hw_cfg) are not reset. host mac reset completion can be determined by polling the hmac_rst bit in the reset control register (reset_ctl) until it clears. 1588 reset a reset of all 1588 related logic, including the clock/ev ent generation and 1588 tsus, is performed by setting the 1588 reset (1588_reset) bit in the 1588 command and control register (1588_cmd_ctl) . the registers described in section 14.0, "ieee 1588," on page 298 are reset. no other modules of the device are affected by this reset. 1588 reset completion can be determined by polling the 1588 reset (1588_reset) bit in the 1588 command and con- trol register (1588_cmd_ctl) until it clears. note: when using the soft reset bit to reset the phy, register bits designated as nasr are not reset. downloaded from: http:///
lan9250 ds00001913a-page 42 ? 2015 microchip technology inc. 6.2.3 reset registers 6.2.3.1 reset control register (reset_ctl) this register contains software controlled resets. offset: 1f8h size: 32 bits note: this register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. if the host interface is in a reset state, returned data may be invalid. it is not necessary to read all four bytes of this register. dword access rules do not apply to this register. bits description type default 31:7 reserved ro - 6 reserved ro - 5 host mac reset (hmac_rst) setting this bit resets the host mac sub-system. when the host mac sub- system is released from reset, this bit is automatically clear ed. all writes to this bit are ignored while this bit is set. note: this bit is not accessible via the eeprom loaders register initialization function ( section 13.4.5 ). r/w sc 0b 4 reserved ro - 3 reserved ro - 2 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 43 lan9250 1 phy reset (phy_rst) setting this bit resets the phy. the internal logic automatically holds the phy reset for a minimum of 102us. when the phy is released from reset, this bit is automatically cleared. all writes to this bit are ignored while this bit is set. note: this bit is not accessible via the eeprom loaders register initialization function ( section 13.4.5 ). r/w sc 0b 0 digital reset (digital_rst) setting this bit resets the complete ch ip except the pll and phy. all system csrs are reset except for any nasr type bits. any in progress eeprom commands (including reload) are terminated. the eeprom loader will automatically reload the configuration following this reset, but will not reset the phy. if desired, the above phy reset can be issued once the device is configured. when the chip is released from reset, this bit is automat ically cleared. all writes to this bit are ignored while this bit is set. note: this bit is not accessible via the eeprom loaders register initialization function ( section 13.4.5 ). r/w sc 0b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 44 ? 2015 microchip technology inc. 6.3 power management the device supports several block and chip level power ma nagement features as well as wake-up event detection and notification. 6.3.1 wake-up event detection 6.3.1.1 host mac wake on lan (wol) the host mac provides the follo wing wake-on-lan detection modes: perfect da (destination address) : this mode, enabled by the perfect da wakeup enable (pfda_en) bit in the host mac wake-up control and status register (hmac_wucsr) , will trigger a wol event when an incom- ing frame has a destination address field that exactly matches the mac address programmed into the mac. the perfect da frame received (pfda_fr) bit in the host mac wake-up control and status register (hmac_wucsr) will be set when pfda_en is set, and a perfect da event occurs. broadcast : this mode, enabled by the broadcast wakeup enable (bcst_en) bit in the host mac wake-up control and status register (hmac_wucsr) , will trigger a wol event when an incoming frame is a broadcast frame. the broadcast frame received (bcast_fr) bit in the host mac wake-up control and status register (hmac_wucsr) will be set when bcst_en is set, and a broadcast event occurs. remote wake-up frame : this mode, enabled by the wake-up frame enable (wuen) bit in the host mac wake-up control and status register (hmac_wucsr) , will trigger a wol event when an incoming frame is accepted based on the wake-up filter registers in the host mac. the remote wake-up frame received (wufr) bit in the host mac wake-up control and status register (hmac_wucsr) will be set when wuen is set, and a remove wake-up frame event occurs. magic packet : this mode, enabled by the magic packet enable (mpen) bit in the host mac wake-up control and status register (hmac_wucsr) , will trigger a wol event when an incoming frame is accepted and is a magic packet. the magic packet received (mpr) bit in the host mac wake-up control and status register (hmac_wucsr) will be set when mpen is set, and a magic packet event occurs. if any of the pfda_fr, bcast_fr, wufr or mpr bits are set, the wake on status (wol_sts) bit of the power man- agement control register (pmt_ctrl) will be set. the wake-on-enable (wol_en) enables this bit as a pme event. in addition, when the power management wakeup (pm_wake) bit in the power management control register (pmt_ctrl) is set, these events can wake up the chip. refer to section 11.6.1, "perfect da detection," on page 144 , section 11.6.2, "broadcast detection," on page 145 , sec- tion 11.6.3, "wake-up frame detection," on page 145 and section 11.6.4, "magic pa cket detection," on page 150 for additional details on these features. 6.3.1.2 phy energy detect energy detect power down mode reduces phy power cons umption. in energy-detect pow er-down mode, the phy will resume from power-down when energy is seen on the cabl e (typically from link pulses) and set the energyon inter- rupt bit in the phy interrupt source flags register (phy_interrupt_source) . refer to section 12.2.10.2, "energy detect power-down," on page 223 for details on the operat ion and configuration of the phy energy-detect power-down mode. if enabled, via the phy interrupt mask register (phy_interrupt_mask) , the phy will generate an interrupt. this interrupt is reflected in the interrupt status register (int_sts) , bit 26 (phy_int). the int_sts register bit will trigger the irq interrupt output pin if enabled, as described in section 8.2.2, "ethernet phy interrupts," on page 63 . the energy-detect phy interrupt will also set the energy-detect status (ed_sts) bit of the power management con- trol register (pmt_ctrl) . the energy-detect enable (ed_en) bit will enable the status bit as a pme event. note: if a carrier is present when energy detect power down is enabled, then detection will occur immediately. note: any phy interrupt will set the above status bits. t he host should only enable the appropriate phy interrupt source in the phy interrupt mask regist er (phy_interrupt_mask) . downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 45 lan9250 6.3.2 wake-up (pme) notification a simplified diagram of the logic that controls the pme output pin and pme interrupt can be seen in figure 6-1 . the pme module handles the latching of the host mac wake on status (wol_sts) bit and the phy energy-detect status (ed_sts) bit in the power management control register (pmt_ctrl) . this module also masks the status bits with the corresponding enable bits ( wake-on-enable (wol_en) and energy- detect enable (ed_en) ) and combines the results together to generate the power management interrupt event (pme_int) status bit in the interrupt status register (int_sts) . the pme_int status bit is then masked with the power management event interrupt enable (pme_int_en) bit and combined with the other interrupt sources to drive the irq output pin. in addition to generating interrupt even ts, the pme event can also drive the pme output pin to indicate wake-up events exclusively. the pme event is enabled with the pme enable (pme_en) in the power management control register (pmt_ctrl) , the pme output pin characteristics can be configured via the pme buffer type (pme_type) , pme indi- cation (pme_ind) and pme polarity (pme_pol) bits of the power management control register (pmt_ctrl) . these bits allow the pme output pin to be open-drain, active high push-pull or active-low push-pull and configure the output to be continuous, or pulse for 50 ms. in system configurations where the pme output pin is shared among multiple devices (wired ored), the wol_sts and ed_sts bits within the pmt_ctrl register can be read to determine which device is driving the pme signal. when the pm_wake bit of the power management control register (pmt_ctrl) is set, the pme event will automat- ically wake up the system in certain chip level power modes, as described in section 6.3.4.2, "exiting low power modes," on page 48 . this is done independent from the values of the pme_en, pme_pol, pme_ind and pme_type register bits. note: note: the pme interrupt status bit (pme_int) in the in t_sts register is set regardless of the setting of pme_int_en. downloaded from: http:///
lan9250 ds00001913a-page 46 ? 2015 microchip technology inc. 6.3.3 block level power management the device supports software controlled clock disabling of various modules in order to reduce power consumption. 6.3.3.1 disabling the host mac the entire host mac may be disabled by setting the hmac_dis bit in the power management control register (pmt_ctrl) . as a safety precaution, in order for this bit to be se t, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. figure 6-1: pme pin and pme interrupt signal generation note: disabling individual blocks does not automatically reset the block, it only places it into a static non-opera- tional state in order to reduce the power consumption of the device. if a block re set is not performed before re-enabling the block, then care must be taken to ensu re that the block is in a state where it can be disabled and then re-enabled. pme ed_en (bit 14) of pmt_ctrl register wol_en (bit 9) of pmt_ctrl register 50ms pme_en (bit 1) of pmt_ctrl register pme_ind (bit 3) of pmt_ctrl register pme_pol (bit 2) of pmt_ctrl register pme_type (bit 6) of pmt_ctrl register logic wuen (bit 2) of hmac_wucsr register mpen (bit 1) of hmac_wucsr register wol_sts (bit 5) of pmt_ctrl register wufr (bit 6) of hmac_wucsr register mpr (bit 5) of hmac_wucsr register denotes a level-triggered "sticky" status bit pme_int_en (bit 17) of int_en register pme_int (bit 17) of int_sts register irq_en (bit 8) of irq_cfg register irq other system interrupts ed_sts (bit 16) of pmt_ctrl register host mac phy power management control int7_mask (bit 7) of phy_interrupt_mask register int7 (bit 7) of phy_interrupt_source register polarity & buffer type logic bcst_en (bit 0) of hmac_wucsr register bcast_fr (bit 4) of hmac_wucsr register pfda_en (bit 3) of hmac_wucsr register pfda_fr (bit 7) of hmac_wucsr register other phy interrupts pm_wake (bit 28) of pmt_ctrl register pme wake-up downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 47 lan9250 the host mac wol detect ion can be left func tioning by using the hm ac_sys_only_dis bit instead, which keeps the rx and tx clocks enabled. as a sa fety precaution, in order for th is bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. 6.3.3.2 disabling the 1588 unit the entire 1588 unit, including the csrs, may be disabled by setting the 1588_dis bit in the power management con- trol register (pmt_ctrl) . as a safety precaution, in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. the timestamp unit, including csrs, may be disabled by setting the appropriate 1588_tsu_dis bit in the power man- agement control register (pmt_ctrl) . as a safety precaution, in order for a bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. 6.3.3.3 phy power down the phy may be placed into power-down as described in section 12.2.10, "phy power-down modes," on page 222 . 6.3.3.4 led pins power down all led outputs may be disabled by setting the led_dis bit in the power management control register (pmt_ctrl) . open-drain / open-source leds are un-driven. push-pull leds are still driven but are set to their inactive state. application note: individual leds can be disabled by setting them open-drain gpio outputs with a data value of 1. 6.3.4 chip level power management the device supports power-down modes to allow applications to minimize power consumption. power is reduced by disabling the clocks as outlined in table 6-2, "power management states" . all configuration data is saved when in any power state. register contents are not af fected unless sp ecifically indicated in the register descrip- tion. there is one normal operating power state, d0, and three power saving states: d1, d2 and d3. although appropriate for various wake-up detection functions, the power states do not directly enable and are not enforced by these functions. d0 : normal mode - this is the normal mode of operation of th is device. in this mode, all functionality is available. this mode is entered automatically on any chip-level reset (por, rst# pin reset). d1 : system clocks disabled, xtal, pll a nd network clocks enabled - in this low power mode, all clocks derived from the pll clock are disabled. the network clocks remain enabled if supplied by the phy. the crystal oscillator and the pll remain enabled. exit from this mode may be done manually or automatically. this mode is useful for mac wol mode, where the ph y is enabled and the mac is configured for wol detection. this mode could be used for phy general power do wn mode and phy energy detect power down mode. d2 : system clocks disabled, pll disable requested, xtal enabled - in this low power mode, all clocks derived from the pll clock are disabled. the pll is allowed to be disabled (and will disable if the phy is in either energy detect or general power down). the network clocks rema in enabled if supplied by the phy. the crystal oscillator remains enabled. exit from this mode may be done manually or automatically. this mode is useful for phy energy detect power down mode. this mode could be used for phy general power down mode. d3 : system clocks disabled, pll disabled, xtal disabled - in this low power mode, all clocks derived from the pll clock are disabled. the pll will be disabled. the crystal oscillator is disabled. ex it from this mode may be only be done manually. this mode is useful for phy general power down mode. the host must place the phy into general power down mode by setting the power down (phy_pwr_dwn) bit of the phy basic control register (phy_basic_control) before setting this power state. downloaded from: http:///
lan9250 ds00001913a-page 48 ? 2015 microchip technology inc. 6.3.4.1 entering low power modes to enter any of the low power modes (d1 - d3) from normal mode (d0), follow these steps: 1. write the pm_mode and pm_wake fields in the power management control register (pmt_ctrl) to their desired values 2. set the wake-up detection desired per section 6.3.1, "wake-up event detection" . 3. set the appropriate wake-up notification per section 6.3.2, "wake-up (pme) notification" . 4. ensure that the device is in a state where it can safely be placed into a low power mode (all packets transmitted, receivers disabled, packets processed / flushed, etc.) 5. set the pm_sleep_en bit in the power management control register (pmt_ctrl) . note: the eeprom loader register data burst sequence ( section 13.4.5 ) can be used to achieve an initial power down state without the need of software by: first setting the phy into general purpose power down by setting the phy_pwr_dwn bit in phy_basic_control indirectly via the hmac_mii_data / hmac_mii_acc via the mac_csr_cmd / mac_csr_data reg- isters. setting the pm_m ode and pm_sleep_en bits in the power management control register (pmt_c- trl) . upon entering any low power mode, the device ready (ready) bit in the hardware configuration register (hw_cfg) and the power management control register (pmt_ctrl) is forced low. 6.3.4.2 exiting low power modes exiting from a low power mode can be done manually or automatically. an automatic wake-up will occur based on the events described in section 6.3.2, "wake-up (pme) notification" . auto- matic wake-up is enabled with the power management wakeup (pm_wake) bit in the power management control register (pmt_ctrl) . a manual wake-up is initiated by the host when: an hbi write ( cs and wr or cs , rd_wr and enb ) is performed to the device. al though all writes are ignored until the device has been woken and a read perfo rmed, the host should direct the write to the byte order test register (byte_test) . writes to any other addresses should not be attempted until the device is awake. an spi/sqi cycle ( scs# low and sck high) is performed to the device. alt hough all reads and writes are ignored until the device has been woken, the host should direct the use a read of the byte order test register (byte_test) to wake the device. reads and writes to an y other addresses should not be attempted until the device is awake. table 6-2: power management states clock source d0 d1 d2 d3 25 mhz crystal oscillator on on on off p l l o no no f f ( 2 )o f f system clocks (100 mhz, 50 mhz, 25 mhz and others) on off off off network clocks available( 1 ) available( 1 ) available( 1 )off( 3 ) note 1: if supplied by the phy 2: pll is requested to be turned off and will disable if the phy is in either energy detect or general power down 3: phy clocks are off note: the pm_mode field cannot be changed at the same time as the pm_sleep_en bit is set and the pm_sleep_en bit cannot be set at the same time that the pm_mode field is changed. note: upon entry into any of the power saving stat es the host interfac es are not functional. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 49 lan9250 to determine when the host interface is functional, the byte order test re gister (byte_test) should be polled. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) or the power management control register (pmt_ctrl) can be polled to determine when the device is fully awake. for both automatic and manual wake-up, the device ready (ready) bit will go high once the device is returned to power savings state d0 and the pll has re-stabilized. the pm_mode and pm_sleep_en fields in the power man- agement control register (pmt_ctrl) will also clear at this point. under normal conditions, the device will wake-up within 2 ms. 6.3.5 power management registers 6.3.5.1 power management control register (pmt_ctrl) this read-write register controls the po wer management features and the pme pin of the device. the ready state of the device be determined via the device ready (ready) bit of this register. offset: 084h size: 32 bits note: this register can be read while the device is in the reset or not ready / power savings states without leaving the host interface in an intermediate state. if the host interface is in a reset state, returned data may be invalid. it is not necessary to read all four bytes of this register. dword access rules do not apply to this register. bits description type default 31:29 power management mode (pm_mode) this register field determines the chip level power management mode that will be entered when the power management sleep enable (pm_sleep_en) bit is set. 000: d0 001: d1 010: d2 011: d3 100: reserved 101: reserved 110: reserved 111: reserved writes to this field are ignored if power management sleep enable (pm_sleep_en) is also being written with a 1. this field is cleared when the device wakes up. r/w/sc 000b downloaded from: http:///
lan9250 ds00001913a-page 50 ? 2015 microchip technology inc. 28 power management sleep enable (pm_sleep_en) setting this bit enters the chip level power management mode specified with the power management mode (pm_mode) field. 0: device is not in a low power sleep state 1: device is in a low power sleep state this bit can not be written at the same time as the pm_mode register field. the pm_mode field must be set, and then this bit must be set for proper device operation. writes to this bit with a value of 1 are ignored if power management mode (pm_mode) is being written with a new value. note: although not prevented by h/w, th is bit should not be written with a value of 1 while power management mode (pm_mode) has a value of d0. this field is cleared when the device wakes up. r/w/sc 0b 27 power management wakeup (pm_wake) when set, this bit enables automatic wake-up based on pme events. 0: manual wakeup only 1: auto wakeup enabled r/w 0b 26 led disable (led_dis) this bit disables led outputs. open-dr ain / open-source leds are un-driven. push-pull leds are still driven but are set to their inactive state. 0: leds are enabled 1: leds are disabled r/w 0b 25 1588 clock disable (1588_dis) this bit disables the clocks for the entire 1588 unit. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b 24:23 reserved ro - 22 1588 timestamp unit clock disable (1588_tsu_dis) this bit disables the clocks for the 1588 timestamp unit. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b 21 reserved ro - 20 reserved ro - bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 51 lan9250 19 host mac clock di sable (hmac_dis) this bit disables the 25 and 100 mhz, rx and tx clocks to the mac. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b 18 host mac system clock only disable (hmac_sys_only_dis) this bit disables the 25 and 100 mhz clocks to the mac but leaves the rx and tx clocks active. 0: clocks are enabled 1: clocks are disabled in order for this bit to be set, it must be written as a 1 two consecutive times. a write of a 0 will reset the count. r/w 0b 17 reserved ro - 16 energy-detect status (ed_sts) this bit indicates an energy detect event occurred on the phy. in order to clear this bit, it is required that the event in the phy be cleared as well. the event sources are described in section 6.3, "power management," on page 44 . r/wc 0b 15 reserved ro - 14 energy-detect enable (ed_en) when set, the pme_int bit in the interrupt status register (int_sts) will be asserted upon an energy-det ect event from the port. when set, the pme output pin (if enabled via the pme_en bit) will also be asserted in accordance with the pme_i nd bit upon an energy-detect event from the port. r/w 0b 13:10 reserved ro - 9 wake-on-enable (wol_en) when set, the pme_int bit in the interrupt status register (int_sts) will be asserted upon a host mac wol event. when set, the pme output pin (if enabled via the pme_en bit) will also be asserted in accordance with the pme_ ind bit upon a host mac wol event. r/w 0b 8:7 reserved ro - 6 pme buffer type (pme_type) when this bit is cleared, the pme output pin functions as an open-drain buf- fer for use in a wired-or configuration. when set, the pme output pin is a push-pull driver. when the pme output pin is configured as an open-drain output, the pme_pol field of this register is ignor ed and the output is always active low. 0: pme pin open-drain output 1: pme pin push-pull driver r/w nasr 0b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 52 ? 2015 microchip technology inc. 5 wake on status (wol_sts) this bit indicates that a wake-up, ma gic packet, perfect da, or broadcast frame was detected by the host mac. in order to clear this bit, it is required that the event in the host mac be cleared as well. the event sources are described in section 6.3, "power management," on page 44 . r/wc 0b 4 reserved ro - 3 pme indication (pme_ind) the pme signal can be configured as a pulsed output or a static signal, which is asserted upon detection of a wake-up event. when set, the pme signal will pulse active for 50ms upon detection of a wake-up event. when cleared, the pme signal is driven cont inuously upon detection of a wake-up event. 0: pme driven continuously on detection of event 1: pme 50ms pulse on detection of event the pme signal can be deactivated by cl earing the above status bit(s) or by clearing the appropriate enable(s). r/w 0b 2 pme polarity (pme_pol) this bit controls the polarity of the pme signal. when set, the pme output is an active high signal. when cleared, it is active low. note: when pme is configured as an open-drain output, this field is ignored and the output is always active low. 0: pme active low 1: pme active high r/w nasr 0b 1 pme enable (pme_en) when set, this bit enables the external pme signal pin. when cleared, the external pme signal is disabled. note: this bit does not affect the pme_int interrupt bit of the interrupt status register (int_sts) . 0: pme pin disabled 1: pme pin enabled r/w 0b 0 device ready (ready) when set, this bit indicates that the device is ready to be accessed. upon power-up, rst# reset, return from power savings states, host mac module level reset or digital reset, the host processor may interrogate this field as an indication that the device has stabilized and is fully active. this rising edge of this bit will assert the device ready (ready) bit in int_sts and can cause an interrupt if enabled. note: with the exception of the hw_cfg, pmt_ctrl, byte_test, and reset_ctl registers, read access to any internal resources is forbidden while the ready bit is cleared. writes to any address are invalid until this bit is set. note: this bit is identical to bit 27 of the hardware configuration register (hw_cfg) . ro 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 53 lan9250 6.4 device ready operation the device supports a ready status register bit that indicates to the host softwa re when the device is fully ready for operation. this bit may be read via the power management contro l register (pmt_ctrl) or the hardware configura- tion register (hw_cfg) . following power-up reset, rst# reset, or digital reset (see section 6.2, "resets" ), the device ready (ready) bit indi- cates that the device has read, and is c onfigured from, the contents of the eeprom. an eeprom reload command, via the eeprom command register (e2p_cmd) , will restart the eeprom loader, temporarily causing the device ready (ready) to be low. a host mac reset, via the reset control register (reset_ctl) , will utilize the eeprom loader, temporarily causing the device ready (ready) to be low. entry into any power savings state (see section 6.3.4, "chip level power management" ) other than d0 will cause device ready (ready) to be low. upon wake-up, the device ready (ready) bit will go high once the device is returned to power savings state d0 and the pll has re-stabilized. downloaded from: http:///
lan9250 ds00001913a-page 54 ? 2015 microchip technology inc. 7.0 configuration straps configuration straps allow various features of the device to be automatically c onfigured to user defined values. config- uration straps can be organized into two main categories: hard-straps and soft-straps . both hard-straps and soft-straps are latched upon power-on reset (por), or pin reset ( rst# ). the primary difference betwe en these strap types is that soft-strap default values can be overridden by the eeprom loa der, while hard-s traps cannot. configuration straps which have a corresponding external pin include internal resistors in order to prevent the signal from floating when unconnected. if a particular configuratio n strap is connected to a load, an external pull-up or pull- down resistor should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. the internal resistor can also be ov erridden by the addition of an external resistor. 7.1 soft-straps soft-strap values are latched on the release of por or rst# and are overridden by values from the eeprom loader (when an eeprom is present). these straps are used as dire ct configuration values or as defaults for cpu registers. some, but not all, soft-straps have an associated pin. those that do not have an associated pin, have a tie off default value. all soft-strap values can be overridden by the eeprom loader. refer to section 13.4, "eepr om loader," on page 290 for information on the opera tion of the eeprom l oader and the loading of strap values. table 13-4, eeprom configuration bits, on page 292 defines the soft-strap eeprom bit map. straps which have an associated pin are also fully defined in section 3.0, "pin descriptions and configuration," on page 10 . table 7-1 provides a list of all soft-straps and their associated pin or default value. upon setting the digital reset (digital_rst) bit in the reset control register (reset_ctl) or upon issuing a reload command via the eeprom command register (e2p_cmd) , these straps return to their original latched (non- overridden) values if an eeprom is no longer attached or has been erased. the associated pins are not re-sampled (i.e. the value latched on the pin during the last por or rst# will be used, not the value on the pin during the digital reset or reload command issuance). if it is desired to re -latch the current configuration strap pin values, a por or rst# must be issued. note: the system designer must guarantee that configuration strap pins meet the timing requirements specified in section 19.6.3, "reset and configuration strap timing" . if configuration strap pins are not at the correct voltage level prior to being latched, the dev ice may capture incorrect strap values. note: the use of the term configures in the description section of ta b l e 7 - 1 indicates the register bit is loaded with the strap value, while the term affects means the value of the register bit is determined by the strap value and some other condition(s). table 7-1: soft-strap config uration strap definitions strap name description pin / default value led_en_strap[2:0] led enable straps: configures the default value for the led enable 2-0 (led_en[2:0]) bits of the led configuration register (led_cfg) . 111b led_fun_strap[2:0] led function straps: configures the default value for the led function 2-0 (led_fun[2:0]) bits of the led configuration register (led_cfg) . 000b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 55 lan9250 hbi_ale_qualification_strap hbi ale qualification strap: configures the hbi interface to qualify the alehi and alelo signals with the cs signal. 0 = address input is latched with alehi and alelo 1 = address input is latched with alehi and alelo only when cs is active 1b hbi_rw_mode_strap hbi read / write mode strap: configures the hbi interface for separate read & write signals or direction and enable sig- nals. 0 = read & write 1 = direction & enable 0b hbi_cs_polarity_strap hbi chip select polarity strap: configures the polarity of the hbi interface chip select signal. 0 = active low 1 = active high 0b hbi_rd_rdwr_polarity_strap hbi read, read / write polarity strap: configures the polar- ity of the hbi interface read signal. 0 = active low read 1 = active high read configures the polarity of the hb i interface read / write signal. 0 = read when 1, write when 0 (r/nw) 1 = write when 1, read when 0 (w/nr) 0b hbi_wr_en_polarity_strap hbi write, enable polarity strap: configures the polarity of the hbi interface write signal. 0 = active low write 1 = active high write configures the polarity of th e hbi interface enable signal. 0 = active low enable 1 = active high enable 0b hbi_ale_polarity_strap hbi ale polarity strap: configures the polarity of the hbi interface alehi and alelo signals. 0 = active low strobe (address saved on rising edge) 1 = active high strobe (address saved on falling edge) 1b 1588_enable_strap 1588 enable strap: configures the default value of the 1588 enable (1588_enable) bit in the 1588 command and con- trol register (1588_cmd_ctl) . 0b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value downloaded from: http:///
lan9250 ds00001913a-page 56 ? 2015 microchip technology inc. auto_mdix_strap_1 phy auto-mdix en able strap: configures the default value of the amdix_en strap state bit of the hardware configura- tion register (hw_cfg) . this strap is also used in conjunction with manual_mdix- _strap_1 to configure phy auto-mdix functionality when the auto-mdix control (amdixctrl) bit in the phy special con- trol/status indication r egister (phy_special_con- trol_stat_ind) indicates the strap settings should be used for auto-mdix configuration. note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b manual_mdix_strap_1 phy manual mdix strap: configures mdi(0) or mdix(1) for the phy when the auto_mdix_strap_1 is low and the auto- mdix control (amdixctrl) bit in the phy special control/ status indication register (phy_special_con- trol_stat_ind) indicates the strap settings are to be used for auto-mdix configuration. note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 0b autoneg_strap_1 phy auto negotiat ion enable strap: configures the default value of the auto-negotiation enable (phy_an) enable bit in the phy basic control regist er (phy_basic_control) . this strap also affects the default value of the following regis- ter bits: speed select lsb (phy_speed_sel_lsb) and duplex mode (phy_duplex) bits of the phy basic control register (phy_basic_control) 10base-t full duplex and 10base-t half duplex bits of the phy auto-negotiation advertisement register (phy_an_adv) phy mode (mode[2:0]) bits of the phy special modes register (phy_special_modes) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 57 lan9250 speed_strap_1 phy speed select strap: this strap affects the default value of the following register bits: speed select lsb (phy_speed_sel_lsb) bit of the phy basic control register (phy_basic_control) 10base-t full duplex and 10base-t half duplex bits of the phy auto-negotiation advertisement register (phy_an_adv) phy mode (mode[2:0]) bits of the phy special modes register (phy_special_modes) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b duplex_strap_1 phy duplex select strap: this strap affects the default value of the following register bits: duplex mode (phy_duplex) bit of the phy basic con- trol register (p hy_basic_control) 10base-t full duplex bit of the phy auto-negotiation advertisement register (phy_an_adv) phy mode (mode[2:0]) bits of the phy special modes register (phy_special_modes) refer to the respective register definition sections for addi- tional information. 1b fd_fc_strap_1 phy full-duplex flow control enable strap: this strap affects the default value of the following register bits: asymmetric pause bit of the phy auto-negotiation advertisement register (phy_an_adv) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b manual_fc_strap_1 phy manual flow control enable strap: this strap affects the default value of the following register bits: asymmetric pause and symmetric pause bit of the phy auto-negotiation advertisement register (phy_an_adv) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 0b table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value downloaded from: http:///
lan9250 ds00001913a-page 58 ? 2015 microchip technology inc. 7.2 hard-straps hard-straps are latched upon power-on reset (por) or pin reset ( rst# ) only. unlike soft-straps, hard-straps always have an associated pin and can not be overridden by the eeprom loader. these straps are us ed as either direct con- figuration values or as register defaults. table 7-2 provides a list of all hard-stra ps and their associated pin. these straps, along with their pin assignments are also fully defined in section 3.0, "pin descriptions and configuration," on page 10 . eee_enable_strap_1 host mac energy efficient ethernet enable strap: config- ures the default value of the host mac energy efficient ether- net (hmac_eee_enable) bit in the section 11.15.1, "host mac control register (hmac_cr)," on page 193 . refer to the respective register definition sections for addi- tional information. 1b eee_enable_strap_1(cont.) phy energy efficient et hernet enable strap: this strap affects the default value of the following register bits: phy energy efficient ethernet enable (phyeeeen) bit of the phyedpd nlp / crossover time / eee configura- tion register (phy_edpd_cfg) 100base-tx eee bit of the phy eee capability regis- ter (phy_eee_cap) 100base-tx eee bit of the phy eee advertisement register (phy_eee_adv) note: this has no effect when the phy is in 100base-fx mode. refer to the respective register definition sections for addi- tional information. 1b table 7-2: hard-strap config uration strap definitions strap name description pins eeprom_size_strap eeprom size strap: configures the eeprom size range. a low selects 1k bits (128 x 8) through 16k bits (2k x 8). a high selects 32k bits (4k x 8) through 512k bits (64k x 8). e2psize table 7-1: soft-strap configurat ion strap definitions (continued) strap name description pin / default value downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 59 lan9250 host_intf_mode_strap host interface mode strap: configures the host manage- ment mode. 0 = spi mode 1 = hbi mode the operating mode results from the following mapping: see ta b l e 7 - 3 for the combined host interface strapping. note: refer to section 2.0, "general description," on page 8 for additional information on the various modes of the device. mngt1 : mngt0 hbi_addr_mode_strap hbi address mode strap: configures the hbi interface for multiplexed or non-multiplexed indexed addressing modes. 0 = multiplexed 1 = non-multiplexed indexed see ta b l e 7 - 3 for the combined host interface strapping. note: refer to section 2.0, "general description," on page 8 for additional information on the various modes of the device. mngt1 hbi_addr_phase_strap hbi address phase strap: configures the number of address cycles for the hbi interface when in multiplexed address mode. 0 = single phase multiplexed 1 = dual phase multiplexed see ta b l e 7 - 3 for the combined host interface strapping. note: refer to section 2.0, "general description," on page 8 for additional information on the various modes of the device. mngt3 table 7-2: hard-strap co nfiguration strap definitions (continued) strap name description pins mngt1 : mngt0 mngt_mode_strap 00 0 (spi) 01, 10 or 11 1 (hbi) downloaded from: http:///
lan9250 ds00001913a-page 60 ? 2015 microchip technology inc. hbi_data_mode_strap[1:0] hbi data mode straps: configures the data width of the hbi interface. 00 = 8-bit 01 = 16-bit 1x = reserved the data mode results from the following mapping: note: effectively, the data mode is determined by mngt2 in multiplexed mode and by mngt0 in non-multiplexed indexed mode. see ta b l e 7 - 3 for the combined host interface strapping. note: refer to section 2.0, "general description," on page 8 for additional information on the various modes of the device. mngt2 : mngt1 : mngt0 fx_mode_strap_1 phy fx mode strap: selects fx mode for the phy. this strap is set high when fxlosen is above 1 v (typ.) or fxsdena is above 1 v (typ.). fxlosen : fxsdena fx_los_strap_1 phy fx-los select strap: selects loss of signal mode for the phy. this strap is set high when fxlosen is above 1 v (typ.). fxlosen table 7-2: hard-strap co nfiguration strap definitions (continued) strap name description pins mngt2 : mngt1 : mngt0 hbi_data_mode_strap x00 (spi) reserved 001 (hbi multiplexed) 00 (8-bit) 101 (hbi multiplexed) 01 (16-bit) x10 (hbi non-multi- plexed indexed) 00 (8-bit) x11 (hbi non-multi- plexed indexed) 01 (16-bit) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 61 lan9250 note 1: the combined host interface strap chart is as follows: table 7-3: hbi strap mapping mngt1 mngt0 mngt3 mngt2 host mode 0 0 x x spi 0100h b i m u l t i p l e x e d 1 p h a s e 8 - b i t 0101h b i m u l t i p l e x e d 1 p h a s e 1 6 - b i t 0110h b i m u l t i p l e x e d 2 p h a s e 8 - b i t 0111h b i m u l t i p l e x e d 2 p h a s e 1 6 - b i t 1 0 x x hbi indexed 8-bit 1 1 x x hbi indexed 16-bit downloaded from: http:///
lan9250 ds00001913a-page 62 ? 2015 microchip technology inc. 8.0 system interrupts 8.1 functional overview this chapter describes the system interrupt structure of the de vice. the device provides a multi-tier programmable inter- rupt structure which is controlled by the system interrupt controller. the pr ogrammable system interrupts are generated internally by the various device sub-modules and can be config ured to generate a single external host interrupt via the irq interrupt output pin. the programmabl e nature of the host interr upt provides the user with the ability to optimize performance dependent upon the ap plication requirements. the irq interrupt buffer type, polarity and de-assertion interval are modifiable. the irq interrupt can be configured as an open-drain output to facilitate the sharing of interrupts with other devices. all internal interrupts are maskable and capable of triggering the irq interrupt. 8.2 interrupt sources the device is capable of generating the following interrupt types: 1588 interrupts ethernet phy interrupts gpio interrupts host mac interrupts (fifos) power management interrupts general purpose timer interrupt (gpt) software interrupt (general purpose) device ready interrupt clock output test mode all interrupts are accessed and configured via registers arra nged into a multi-tier, branch -like structure, as shown in figure 8-1 . at the top level of the devic e interrupt structure are the interrupt status register (int_sts) , interrupt enable register (int_en) and interrupt configuration register (irq_cfg) . the interrupt status register (int_sts) and interrupt enable register (int_en) aggregate and enable/disable all inter- rupts from the various device sub-modules, combining them together to create the irq interrupt. these registers pro- vide direct interrupt access/configuration to the host mac, general purpose timer, software and device ready interrupts. these interrupts can be monitored, enabled/disabled and cleared, directly within th ese two registers. in addi- tion, event indications are provided fo r the 1588, power management, gpio and ethernet phy interrupts. these inter- rupts differ in that the interrupt sources are generated a nd cleared in other sub-block r egisters. the int_sts register does not provide details on what specific event within the sub-module caused the interrupt and requires the software to poll an additional sub-module interrupt register (as shown in figure 8-1 ) to determine the exact interrupt source and clear it. for interrupts which involve multiple registers, only after the interrupt has been serviced and cleared at its source will it be cleared in the int_sts register. the interrupt configuration register (irq_cfg) is responsible for enabling/disabling the irq interrupt output pin as well as configuring its properties. the irq_ cfg register allows the modification of the irq pin buffer type, polarity and de-assertion interval. the de-assertion timer guarant ees a minimum interrupt de-assertion period for the irq output and is programmable via the interrupt de-assertio n interval (int_deas) field of the interrupt configuration register (irq_cfg) . a setting of all zeros disables the de-assertion timer. the de-assertion interval starts when the irq pin de- asserts, regardless of the reason. note: the de-assertion timer does not apply to the pme interrupt. the pme interrupt is ored into the irq logic following the deassertion timer gating. assertion of the pme interrupt does not affect the de-assertion timer. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 63 lan9250 the following sections detail each category of interrupts and their related registers. refer to the corresponding functions chapter for bit-level definitions of all interrupt registers. 8.2.1 1588 interrupts multiple 1588 time stamp interrupt sources are provided by the device. the top-level 1588 interrupt event (1588_evnt) bit of the interrupt status register (int_sts) provides indication that a 1588 interrupt event occurred in the 1588 interrupt status register (1588_int_sts) . the 1588 interrupt enable register (1588_int_en) provides enabling/disabling of all 1588 interrupt conditions. the 1588 interrupt status register (1588_int_sts) provides the status of all 1588 interrupts. these include tx/rx 1588 clock capture indication, 1588 clock capture for gpio events, as well as 1588 timer interrupt indication. in order for a 1588 interrupt event to trigger the external irq interrupt pin, the desir ed 1588 interrupt event must be enabled in the 1588 interrupt enable register (1588_int_en) , bit 29 (1588_evnt_en) of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the of the interrupt con- figuration register (irq_cfg) . for additional details on the 1588 time stamp interrupts, refer to section 14.0, "ieee 1 588," on page 298 . 8.2.2 ethernet phy interrupts the top-level phy interrupt event (phy_int) bit of the interrupt status register (int_sts) provides indication that a phy interrupt event occurred in the phy interrupt source flags register (phy_interrupt_source) . phy interrupts are enabled/disabled via their respective phy interrupt mask register (phy_interrupt_mask) . the source of a phy interrupt can be determined and cleared via the phy interrupt source flag s register (phy_inter- rupt_source) . unique interrupts are generated based on the following events: energyon activated auto-negotiation complete remote fault detected link down (link status negated) figure 8-1: functional interrupt hierarchy int_cfg int_sts int_en top level interrupt registers (system csrs) bit 29 (1588_evnt) of int_sts register phy_interrupt_source phy_interrupt_mask phy interrupt registers bit 26 (phy_int) of int_sts register pmt_ctrl power management control register bit 17 (pme_int) of int_sts register gpio_int_sts_en gpio interrupt register bit 12 (gpio) of int_sts register 1588_int_sts 1588_int_en 1588 time stamp interrupt registers downloaded from: http:///
lan9250 ds00001913a-page 64 ? 2015 microchip technology inc. link up (link status asserted) auto-negotiation lp acknowledge parallel detection fault auto-negotiation page received in order for an interrupt event to trigger the external irq interrupt pin, the desired phy interrupt event must be enabled in the corresponding phy interrupt mask regi ster (phy_interrupt_mask) , the phy interrupt event enable (phy_int_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configurati on register (irq_cfg) . for additional details on the ethernet phy interrupts, refer to section 12.2.9, "phy interrupts," on page 220 . 8.2.3 gpio interrupts each gpio of the device is provid ed with its own interrupt. the top-level gpio interrupt event (gpio) bit of the interrupt status register (int_sts) provides indication that a gpio interrupt event occurred in the general purpose i/o interrupt status and enable register (gpio_int_sts_en) . the general purpose i/o interrupt status and enable register (gpi- o_int_sts_en) provides enabling/disabling and status of each gpio interrupt. in order for a gpio interrupt event to trigger the external irq interrupt pin, the desired gpio interrupt must be enabled in the general purpose i/o interrupt status an d enable register (gpio_int_sts_en) , the gpio interrupt event enable (gpio_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configuration register (irq_cfg) . for additional details on the gpio interrupts, refer to section 16.2.1, "gpio interrupts," on page 384 . 8.2.4 host mac interrupts the top-level interrupt status register (int_sts) and interrupt enable register (int_en) provide the status and enabling/disabling of multiple host mac related interrupt s. all host mac interrupts are monitored and configured directly within these two registers. the followi ng host mac related interrupt events are supported: tx stopped rx stopped rx dropped frame counter halfway tx ioc rx dma tx status fifo overflow receive watchdog time-out receiver error transmitter error tx data fifo overrun tx data fifo available tx status fifo full tx status fifo level rx dropped frame rx status fifo full rx status fifo level in order for a host mac interrupt event to trigger the external irq interrupt pin, the desired host mac interrupt event must be enabled in the interrupt enable register (int_en) and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configurati on register (irq_cfg) . refer to the interrupt status register (int_sts) on page 69 and section 11.0, "host mac," on page 139 for additional information on bit definitions and host mac operation. 8.2.5 power management interrupts multiple power management event interrupt sources are provided by the device. the top-level power management interrupt event (pme_int) bit of the interrupt status register (int_sts) provides indication that a power management interrupt event occurred in the power management control register (pmt_ctrl) . downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 65 lan9250 the power management control register (pmt_ctrl) provides enabling/disabling and status of all power manage- ment conditions. these include energy -detect on the phy and wake-on-lan (p erfect da, broadcast, wake-up frame or magic packet) detection by the host mac. in order for a power management interr upt event to trigger the external irq interrupt pin, the desired power manage- ment interrupt event must be enabled in the power management control register (pmt_ctrl) , the power manage- ment event interrupt enable (pme_int_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit 8 of the interrupt configurati on register (irq_cfg) . the power management interrupts are only a portion of the power management features of the device. for additional details on power management, refer to section 6.3, "power management," on page 44 . 8.2.6 general purpose timer interrupt a gp timer (gpt_int) interrupt is provided in the top-level interrupt status register (int_sts) and interrupt enable register (int_en) . this interrupt is issued when the general purpose timer count register (gpt_cnt) wraps past zero to ffffh and is cleared when the gp timer (gpt_int) bit of the interrupt status register (int_sts) is written with 1. in order for a general purpose timer in terrupt event to trigger the external irq interrupt pin, the gpt must be enabled via the general purpose timer enable (timer_en) bit in the general purpose timer configuration register (gpt_cfg) , the gp timer interrupt enable (gpt_int_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configuration register (irq_cfg) . for additional details on the general purpose timer, refer to section 15.1, "general purpose timer," on page 380 . 8.2.7 software interrupt a general purpose software interrupt is provided in the top level interrupt status register (int_sts) and interrupt enable register (int_en) . the software interrupt (sw_int) bit of the interrupt status register (int_sts) is generated when the software interrupt enable (sw_int_en) bit of the interrupt enable register (int_en) changes from cleared to set (i.e. on the rising edge of the enable). this interrupt provides an easy way for software to generate an interrupt and is designed for general software usage. in order for a software interrupt event to trigger the external irq interrupt pin, the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configurati on register (irq_cfg) . 8.2.8 device ready interrupt a device ready interrupt is provided in the top-level interrupt status register (int_sts) and interrupt enable register (int_en) . the device ready (ready) bit of the interrupt status register (int_sts) indicates that the device is ready to be accessed after a power-up or reset condition. writing a 1 to this bit in the interrupt status register (int_sts) will clear it. in order for a device ready interrupt event to trigger the external irq interrupt pin, the device ready enable (ready_en) bit of the interrupt enable register (int_en) must be set and the irq output must be enabled via the irq enable (irq_en) bit of the interrupt configurati on register (irq_cfg) . 8.2.9 clock output test mode in order to facilitate system level debug, the crystal clock can be enabled onto the irq pin by setting the irq clock select (irq_clk_select) bit of the interrupt configuration register (irq_cfg) . the irq pin should be set to a push-pull driver by using the irq buffer type (irq_type) bit for the best result. 8.3 interrupt registers this section details the directly addressable interrupt rela ted system csrs. these register s control, configure and mon- itor the irq interrupt output pin and the various device interrupt sources. for an over view of the entire directly address- able register map, refer to section 5.0, "register map," on page 29 . table 8-1: interrupt registers address register name (symbol) 054h interrupt configuration register (irq_cfg) downloaded from: http:///
lan9250 ds00001913a-page 66 ? 2015 microchip technology inc. 058h interrupt status register (int_sts) 05ch interrupt enable register (int_en) table 8-1: interrupt registers (continued) address register name (symbol) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 67 lan9250 8.3.1 interrupt configurat ion register (irq_cfg) this read/write register c onfigures and indicates the state of the irq signal. offset: 054h size: 32 bits bits description type default 31:24 interrupt de-assertion interval (int_deas) this field determines the interrupt request de-assertion interval in multiples of 10 microseconds. setting this field to zero causes the device to disable the int_deas interval, reset the interval counter and issue any pending interrupts. if a new, non-zero value is written to this field, any subsequent interrupts will obey the new set- ting. this field does not apply to the pme_int interrupt. r/w 00h 23:15 reserved ro - 14 interrupt de-assertion interval clear (int_deas_clr) writing a 1 to this register clears the de-assertion counter in the interrupt controller, thus causing a new de-assertion interval to begin (regardless of whether or not the interrupt controller is currently in an active de-assertion interval). 0: normal operation 1: clear de-assertion counter r/w sc 0h 13 interrupt de-assertion status (int_deas_sts) when set, this bit indicates that the inte rrupt controller is currently in a de- assertion interval and potential interrup ts will not be sent to the irq pin. when this bit is clear, the interrupt cont roller is not currently in a de-assertion interval and interrupts will be sent to the irq pin. 0: interrupt controller not in de-assertion interval 1: interrupt controller in de-assertion interval ro 0b 12 master interrupt (irq_int) this read-only bit indicates the state of the internal irq line, regardless of the setting of the irq_en bit, or the stat e of the interrupt de-assertion function. when this bit is set, one of the enabled interrupts is currently active. 0: no enabled interrupts active 1: one or more enabled interrupts active ro 0b 11:9 reserved ro - 8 irq enable (irq_en) this bit controls the final interrupt out put to the irq pin. when clear, the irq output is disabled and permanently de-asserted. this bit has no effect on any internal interrupt status bits. 0: disable output on irq pin 1: enable output on irq pin r/w 0b 7:5 reserved ro - downloaded from: http:///
lan9250 ds00001913a-page 68 ? 2015 microchip technology inc. note 1: register bits designated as nasr are not reset when the digital_rst bit in the reset control register (reset_ctl) is set. 4 irq polarity (irq_pol) when cleared, this bit enables the irq lin e to function as an active low out- put. when set, the irq output is acti ve high. when the irq is configured as an open-drain out put (via the irq_type bit), this bit is ig nored and the inter- rupt is always active low. 0: irq active low output 1: irq active high output r/w nasr note 1 0b 3:2 reserved ro - 1 irq clock select (irq_clk_select) when this bit is set, the crystal clock ma y be output on the irq pin. this is intended to be used for system debug purposes in order to observe the clock and not for any functional purpose. note: when using this bit, the irq pin should be set to a push-pull driver. r/w 0b 0 irq buffer type (irq_type) when this bit is cleared, the irq pin functions as an open-drain output for use in a wired-or interrupt configurati on. when set, the irq is a push-pull driver. note: when configured as an open-drain output, the irq_pol bit is ignored and the interrupt output is always active low. 0: irq pin open-drain output 1: irq pin push-pull driver r/w nasr note 1 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 69 lan9250 8.3.2 interrupt status register (int_sts) this register contains the current status of the generated interrupts. a value of 1 indicates the corresponding interrupt conditions have been met, while a value of 0 indicates the inte rrupt conditions have not been met. the bits of this register reflect the status of the interrupt sour ce regardless of whether the source has been enabled as an interrupt in the inter- rupt enable register (int_en) . where indicated as r/wc, writing a 1 to the corresponding bits acknowledges and clears the interrupt. offset: 058h size: 32 bits bits description type default 31 software interrupt (sw_int) this interrupt is generated when the software interrupt enable (sw_int_en) bit of the interrupt enable register (int_en) is set high. writing a one clears this interrupt. r/wc 0b 30 device ready (ready) this interrupt indicates that the device is ready to be accessed after a power-up or reset condition. r/wc 0b 29 1588 interrupt event (1588_evnt) this bit indicates an interrupt event from the ieee 1588 module. this bit should be used in conjunction with the 1588 interrupt status register (1588_int_sts) to determine the source of the interrupt event within the 1588 module. ro 0b 28 reserved ro - 27 reserved ro - 26 phy interrupt event (phy_int) this bit indicates an interrupt event from phy. the source of the interrupt can be determined by polling the phy interrupt source flags register (phy_interrupt_source) . ro 0b 25 tx stopped (txstop_int) this interrupt is issued when the stop transmitter (stop_tx) bit in trans- mit configuration register (tx_cfg) is set and the host mac transmitter is halted. r/wc 0b 24 rx stopped (rxstop_int) t his interrupt is issued when the receiver enable (rxen) bit in host mac control register (hmac_cr) is cleared and the host mac receiver is halted. r/wc 0b 23 rx dropped frame counter halfway (rxdfh_int) this interrupt is issued when the host mac rx dropped frames counter register (rx_drop) counts past its halfwa y point (7fffffffh to 80000000h). r/wc 0b 22 reserved ro - 21 tx ioc interrupt (tx_ioc) this interrupt is generated when a buffer with the ioc flag set has been fully loaded into the tx data fifo. r/wc 0b downloaded from: http:///
lan9250 ds00001913a-page 70 ? 2015 microchip technology inc. 20 rx dma interrupt (rxd_int) this interrupt is issued when the amount of data programmed in the rx dma count (rx_dma_cnt) field of the receive configuration register (rx_cfg) has been transferred out of the rx data fifo. r/wc 0b 19 gp timer (gpt_int) this interrupt is issued when the general purpose timer count register (gpt_cnt) wraps past zero to ffffh. r/wc 0b 18 reserved ro - 17 power management inte rrupt event (pme_int) this interrupt is issued when a power management event is detected as configured in the power management control register (pmt_ctrl) . this interrupt functions independent of the pm e signal and will still function if the pme signal is disabled. writing a '1' clear s this bit regardless of the state of the pme hardware signal. in order to clear this bit, all unmasked bits in the power management control register (pmt_ctrl) must first be cleared. note: the interrupt de-assertion interval does not apply to the pme interrupt. r/wc 0b 16 tx status fifo overflow (txso) this interrupt is generated when the tx status fifo overflows. r/wc 0b 15 receive watchdog time-out (rwt) this interrupt is generated when a fram e greater than or equal to 2048 bytes has been received by the host mac. fr ames greater than or equal to 2049 bytes are truncated to 2048 bytes. r/wc 0b 14 receiver error (rxe) indicates that the host mac receiver has encountered an error. please refer to section 11.12.5, "receiver errors," on page 174 for a description of the conditions that will cause an rxe. r/wc 0b 13 transmitter error (txe) when generated, indicates that the host mac transmitter has encountered an error. please refer to section 11.11.7, "transmitter errors," on page 170 for a description of the cond itions that will cause a txe. r/wc 0b 12 gpio interrupt event (gpio) this bit indicates an interrupt event from the general purpose i/o. the source of the interrupt can be determined by polling the general purpose i/ o interrupt status and enable register (gpio_int_sts_en) ro 0b 11 reserved ro - 10 tx data fifo overrun interrupt (tdfo) this interrupt is generated when the tx data fifo is full and another write is attempted. r/wc 0b 9 tx data fifo available interrupt (tdfa) this interrupt is generated when the tx data fifo available space is greater than the programmed level in the tx data available level field of the fifo level interrupt register (fifo_int) . r/wc 0b 8 tx status fifo full interrupt (tsff) this interrupt is generated when the tx status fifo is full. r/wc 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 71 lan9250 7 tx status fifo level interrupt (tsfl) this interrupt is generated when th e tx status fifo reaches the pro- grammed level in the tx status level field of the fifo level interrupt reg- ister (fifo_int) . r/wc 0b 6 rx dropped frame interrupt (rxdf_int) this interrupt is issued whenever a receive frame is dropped by the host mac. r/wc 0b 5 reserved ro - 4 rx status fifo full interrupt (rsff) this interrupt is generated when the rx status fifo is full and another sta- tus write is attempted by the device. r/wc 0b 3 rx status fifo level interrupt (rsfl) this interrupt is generated when the rx status fifo reaches the pro- grammed level in the rx status level field of the fifo level interrupt reg- ister (fifo_int) . r/wc 0b 2:1 reserved ro - 0 reserved ro - bits description type default downloaded from: http:///
lan9250 ds00001913a-page 72 ? 2015 microchip technology inc. 8.3.3 interrupt enable register (int_en) this register contains the interrupt enables for the irq output pin. writing 1 to any of the bits enables the corresponding interrupt as a source for irq . bits in the interrupt status register (int_sts) register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this regi ster (with the exception of soft- ware interrupt enable (sw_int_en) . for descriptions of each interrupt, refer to the interrupt status register (int_sts) bits, which mimic the lay out of this register. offset: 05ch size: 32 bits bits description type default 31 software interrupt enable (sw_int_en) r/w 0b 30 device ready enable (ready_en) r/w 0b 29 1588 interrupt event enable (1588_evnt_en) r/w 0b 28:27 reserved ro - 26 phy interrupt event enable (phy_int_en) r/w 0b 25 tx stopped interrupt enable (txstop_int_en) r/w 0b 24 rx stopped interrupt enable (rxstop_int_en) r/w 0b 23 rx dropped frame counter halfway interrupt enable (rxdfh_int_en) r/w 0b 22 reserved ro - 21 tx ioc interrupt enable (tioc_int_en) r/w 0b 20 rx dma interrupt enable (rxd_int_en) r/w 0b 19 gp timer interrupt enable (gpt_int_en) r/w 0b 18 reserved ro - 17 power management event inte rrupt enable (pme_int_en) r/w 0b 16 tx status fifo overflow interrupt enable (txso_en) r/w 0b 15 receive watchdog time-out interrupt enable (rwt_int_en) r/w 0b 14 receiver error interrupt enable (rxe_int_en) r/w 0b 13 transmitter error interr upt enable (txe_int_en) r/w 0b 12 gpio interrupt event enable (gpio_en) r/w 0b 11 reserved ro - 10 tx data fifo overrun interrupt enable (tdfo_en) r/w 0b 9 tx data fifo available interrupt enable (tdfa_en) r/w 0b 8 tx status fifo full interrupt enable (tsff_en) r/w 0b 7 tx status fifo level interrupt enable (tsfl_en) r/w 0b 6 rx dropped frame interrupt enable (rxdf_int_en) r/w 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 73 lan9250 5 reserved ro - 4 rx status fifo full interrupt enable (rsff_en) r/w 0b 3 rx status fifo level interrupt enable (rsfl_en) r/w 0b 2:1 reserved ro - 0 reserved ro - bits description type default downloaded from: http:///
lan9250 ds00001913a-page 74 ? 2015 microchip technology inc. 9.0 host bus interface 9.1 functional overview the host bus interface (hbi) module provides a high-spee d asynchronous slave interface that facilitates communica- tion between t he device and a host system. the hb i allows access to the system csrs and internal fifos and mem- ories and handles byte swapping based on the endianness select. the following is an overview of t he functions provided by the hbi: address bus input: two addressing modes are supported. these ar e a multiplexed address / data bus and a de- multiplexed address bus with address index register acce sses. the mode selection is done through a configura- tion input. selectable data bus width: the host data bus width is selectable. 16 and 8-bit data modes are supported. this selection is done through a configuration input. th e hbi performs byte and word to dword assembly on write data and keeps track of the byte / word count for reads. individual byte access in 16-bit mode is not supported. selectable read / write control modes: two control modes are available. separate read and write pins or an enable and direction pin. the mode selection is done through a configuration input. selectable control line polarity: the polarity of the chip select, read / write and address latch signals is select- able through configuration inputs. dynamic endianness control: the hbi supports the selection of big an d little endian host byte ordering based on the endianness signal. this highly flexible interface provides mixed endian access for registers and memory. depending on the addressing mode of the device, this signal is either configuration register controlled or as part of the strobed address input. direct fifo access: a fifo direct select signal directs all host write operations to the tx data fifo and all host read operations from the rx data fifo . depending on th e addressing mode of the device, this signal is either directly provided by the host or is st robed as part of the address input. when used with the indexed addressing mode, burst r ead access is supported by toggling the lower address bits. 9.2 read / write control signals the device supports two distinct read / write signal methods: read ( rd ) and write ( wr ) strobes are input on separate pins. read and write signals are decoded from an enable input ( enb ) and a direction input ( rd_wr ). 9.3 control line polarity the device supports polarity control on the following: chip select input ( cs ) read strobe ( rd ) / direction input ( rd_wr ) write strobe ( wr ) / enable input ( enb ) address latch control ( alelo and alehi ) 9.4 multiplexed address / data mode in multiplexed address / data mode, the address, fifo direct select and endia nness select inputs are shared with the data bus. two methods are supported, a single phase addr ess, utilizing up to 16 address / data pins and a dual phase address, utilizing only the lower 8 data bits. 9.4.1 address latch cycles 9.4.1.1 single phase address latching in single phase mode, all address bits, the fifo direct sele ct signal and the endianness select are strobed into the device using the trailing edge of the alelo signal. the address latch is implemented on all 16 address / data pins. in 8-bit data mode, where pins ad[15:8] are used exclusively for addressing, it is not necessary to drive these upper address lines with a valid address continually through read an d write operations. however, this operation, referred to as partial address multiplexing, is acceptable since the device will never drive these pins. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 75 lan9250 qualification of the alelo signal with the cs signal is selectable. when qualification is enabled, cs must be active during alelo in order to strobe the address input s. when qualification is not enabled, cs is a dont care during the address phase. the address is retained for all future read and write operations . it is retained until either a reset event occurs or a new address is loaded. this allows multiple read and write requ ests to take place to the same address, without requiring multiple address latching operations. 9.4.1.2 dual phase address latching in dual phase mode, the lower 8 address bits are strobed into the device using the inactive going edge of the alelo signal and the remaining upper address bits, the fifo direct select signals and the endianness select are strobed into the device using the trailing edge of the alehi signal. the strobes can be in eit her order. in 8-bit data mode, pins ad[15:8] are not used. in 16-bit data mode, pins d[15:8] are used only for data. qualification of the alelo and alehi signals with the cs signal is selectable. when qualification is enabled, cs must be active during alelo and alehi in order to strobe the address inpu ts. when qualification is not enabled, cs is a dont care during the address phase. the address is retained for all future read and write operations . it is retained until either a reset event occurs or a new address is loaded. this allows multiple read and write requ ests to take place to the same address, without requiring multiple address latching operations. 9.4.1.3 address bit to address / data pin mapping in 8-bit data mode, address bit 0 is multiplexed onto pin ad[0] , address bit 1 onto pin ad[1] , etc. the highest address bit is bit 9 and is multiplexed onto pin ad[9] (single phase) or ad[1] (dual phase). the address latched into the device is considered a byte address and covers 1k bytes (0 to 3ffh). in 16-bit data mode, address bit 1 is multiplexed onto pin ad[0] , address bit 2 onto pin ad[1] , etc. the highest address bit is bit 9 and is multiplexed onto pin ad[8] (single phase) or ad[0] (dual phase). the address latched into the device is considered a word address and covers 512 words (0 to 1ffh). when the address is sent to the rest of t he device, it is converted to a byte address. 9.4.1.4 endianness select to address / data pin mapping the endianness select is included into the multiplexed address to allow the host system to dynamically select the endi- anness based on the memory address used. this allows for mixed endian access for registers and memory. the endianness selection is multiplexed to the data pin one bit above the last address bit. 9.4.1.5 fifo direct select to address / data pin mapping the fifo direct select signal is included into the multiple xed address to allow the host system to address the tx and rx data fifos as if they were a large flat address space. the fifo direct select signal is multiplexed to the data pin two bits above the last address bit. 9.4.2 data cycles the host data bus can be 16 or 8-bits wide while all internal registers are 32 bits wide. the host bus interface performs the conversion from words or bytes to dword, while in 8 or 16-bit data mode. two or four contiguous accesses within the same dword are required in order to perform a write or read. 9.4.2.1 write cycles a write cycle occurs when cs and wr are active (or when enb is active with rd_wr indicating write). the host address and endianness were al ready captured during the address latch cycle. on the trailing edge of the write cycle (either wr or cs or enb going inactive), the host data is captured into registers in the hbi. depending on the bus width, either a word or a byt e is captured. for 8 or 16-b it data modes, this functions as the dword assembly with the affected word or byte determined by the lower address inputs. byte swapping is also done at this point based on the endianness. writes following initialization following device initialization, writes from the host bus are ignored until after a read cycle is performed. writes during and foll owing power management downloaded from: http:///
lan9250 ds00001913a-page 76 ? 2015 microchip technology inc. during and following any power management mode other than d0, writes from the host bu s are ignored until after a read cycle is performed. 8 and 16-bit access while in 8 or 16-bit data mode, the host is required to perfo rm two or four, 16 or 8-bit writes to complete a single dword transfer. no ordering requirements exist. the host can acce ss either the low or high word or byte first, as long as the other write(s) is(are) performed to the remaining word or bytes. a write byte / word counter keeps track of the number of writes. at the traili ng edge of the write cycle, the counter is incremented. once all writes occur, a 32-bit write is performed to the internal register. the write byte / word counter is reset if the power management mode is set to anything other than d0. 9.4.2.2 read cycles a read cycle occurs when cs and rd are active (or when enb is active with rd_wr indicating read). the host address and endianness were al ready captured during the address latch cycle. at the beginning of the read cycle, the app ropriate register is select ed and its data is driven onto the data pins. depend- ing on the bus width, either a word or a byte is read. fo r 8 or 16-bit data modes, the returned byte or word is determined by the endianness and the lower address inputs. polling for initialization complete before device initialization, the hbi will not return valid data. to determine when the hbi is functional, the byte order test register (byte_test) should be polled. each poll should consist of an address latch cycle(s) and a data cycle. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. reads during and following power management during any power management mode other than d0, reads from the host bus are ignor ed. if the power management mode changes back to d0 during an active read cycle, the tail end of the read cycle is ignor ed. internal registers are not affected and the state of the hbi does not change. 8 and 16-bit access for certain register accesses, the host is required to perfor m two or four consecutive 16 or 8-bit reads to complete a single dword transfer. no ordering requirements exist. the host can access either the low or high word or byte first, as long as the other read(s) is(are) performed from the remaining word or bytes. a read byte / word counter keeps track of the number of r eads. this counter is sepa rate from the write counter above. at the trailing edge of the read cycle, the counter is incremented. on the last read for the dword, an internal read is performed to update any change on read csrs. the read byte / word counter is reset if the power management mode is set to anything other than d0. special csr handling live bits any register bit that is updated by a h/ w event is held at the beginning of th e read cycle to preven t it from changing during the read cycle. multiple byte / word live registers in 16 or 8-bit modes some registers have live fields or related fields that span across multiple bytes or words. for 16 and 8-bit data reads, it is possible for the value of these fields to ch ange between host read cycles. in order to prevent reading inter- mediate values, these registers are locked when the first byte or word is read and unlocked when the last byte or word is read. the registers are unlocked if the power managem ent mode is set to anything other than d0. note: writing the same word or bytes in the same dw ord assemble cycle may c ause undefined or unde- sirable operation. the hbi hardware does not protect against this operation. note: reading the same word or bytes from the same dword may cause undefined or undesirable opera- tion. the hbi hardware does not pr otect against this operation. the hbi simply counts that four bytes have been read. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 77 lan9250 change on read registers and fifos fifos or change on read registers, ar e updated at the end of the read cycle. for 16 and 8-bit modes, only one internal read cycle is indicated and occurs for the last byte or word. change on read live register bits as described above, registers with live bits are held starting at the beginning of the read cycle and those that have mul- tiple bits that span across bytes or words are also locke d for 16 and 8-bit accesses. although a h/w event that occurs during the hold or lock time would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) at the end of the read cycle and the h/w event would be lost. in order to prevent this, the individual csrs defer the h/w event update until after the read or multiple reads. register polling during reset or initialization some registers support polling during reset or device initializa tion to determine when the device is accessible. for these registers, only one read may be per formed without the need to read the ot her word or bytes. the same byte or word of the register may be re-read repeatedly. a register that is 16 or 8-bit readable or readable during rese t or device initialization, is not ed in its register description . 9.4.2.3 host endianness the device supports big and little endian host byte ordering based upon the endianness select that is latched during the address latch cycle. when the endianness select is low, host access is little endian and when high, host access is big endian. in a typical application the endianness select is con nected to a high-order address line, making endian selection address-based. this highly flexible interface provides mix ed endian access for registers and memory for both pio and host dma access. all internal busses are 32-bit with little endian byte orderi ng. logic within the host bus interface re-orders bytes based on the appropriate endianness bit, and the stat e of the least significant address bits. data path operations for the supported endian conf igurations and data bus sizes are illustrated in figure 9-1: little endian ordering on page 78 and figure 9-2: big endian ordering on page 79 . downloaded from: http:///
lan9250 ds00001913a-page 78 ? 2015 microchip technology inc. figure 9-1: little endian ordering 8-bit little endian 0 1 2 3 0 1 2 3 0 7 0 78 15 16 23 31 24 a = 2 a = 3 msb lsb host data bus internal order a = 0 a = 1 16-bit little endian 0 1 2 3 0 1 2 3 0 78 15 0 78 15 16 23 31 24 a = 0 a = 1 msb lsb host data bus internal order downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 79 lan9250 figure 9-2: big endian ordering 8-bit big endian 0 1 2 3 0 78 15 16 23 31 24 3 2 1 0 0 7 a = 2 a = 3 msb lsb host data bus internal order a = 1 a = 0 16-bit big endian 0 1 2 3 0 78 15 16 23 31 24 3 2 1 0 0 78 15 a = 0 a = 1 msb lsb host data bus internal order downloaded from: http:///
lan9250 ds00001913a-page 80 ? 2015 microchip technology inc. 9.4.3 tx and rx fifo access 9.4.3.1 tx and rx status fifo peek address access normal read access to the tx or rx status fifo causes the fifo to advance to its next entry. for access to the tx and rx status fifo peek addresses, the fifo d oes not advance to its next entry. 9.4.3.2 fifo direct select access a fifo direct select signal is provided allows the host syst em to address the tx and rx data fifos as if they were a large flat address space. when the fifo direct select si gnal, which was latched during the address latch cycle, is active all host write operations are to the tx data fifo and all host read operations are from the rx data fifo. only the lower latched address signals are decoded in order to select t he proper byte or word. all other address inputs are ignored in this mode. all other opera tions are the same (dword a ssembly, fifo popping, etc.). the endianness of fifo direct select accesses is determin ed by the endianness select that was latched during the address latch cycle. burst access when reading the rx data fifo is not supported . however, since the fifo direct select signal is retained until either a reset event occurs or a new address is loaded, multiple read or write requests can occur without requiring multiple address latching operations. 9.4.4 multiplexed addr essing mode function al timing diagrams the following timing diagrams illustrate example multiplexed addressing mode read and write cycles for various address/data configurations and bus sizes. these diagrams do not cover every supported host bus permutation, but are selected to detail the main configuration differences (bus si ze, dual/single phase address latching) within the multiplexed addressing mode of operation. the following should be noted for the timing diagrams in this section: the diagrams in this section depict active-high alehi / alelo , cs , rd , and wr signals. the polarities of these signals are selectable via the hbi_ale_polarity_strap , hbi_cs_polarity_strap , hbi_rd_rdwr_polarity_strap , and hbi_wr_en_polarity_strap , respectively. refer to section 9.3, "control line polarity," on page 74 for additional details. the diagrams in this section depict little endian byte or dering. however, dynamic big and little endianess are sup- ported via the endianess signal. endianess changes only th e order of the bytes involved, and not the overall tim- ing requirements. refer to section 9.4.1.4, "endianness select to address / data pin mapping," on page 75 for additional information. the diagrams in section 9.4.4.1, "dual phase address latching" and section 9.4.4.2, "single phase address latching" utilize rd and wr signals. alternative rd_wr and enb signaling is also supported, as shown in sec- tion 9.4.4.3, "rd_wr / en b control mode examples" . the hbi read/write mode is selectable via the hbi_rw_- mode_strap . the polarities of the rd_wr and enb signals are selectable via the hbi_rd_rdwr_polarity_strap , and hbi_wr_en_polarity_strap . qualification of the alelo and/or alehi with the cs signal is selectable via the hbi_ale_qualification_strap . refer to section 9.4.1.1, "s ingle phase address latching," on page 74 and section 9.4.1.2, "dual phase address latching," on page 75 for additional information. in dual phase address latching mode, the alehi and alelo cycles can be in any order. either or both alelo and alehi cycles maybe skipped and the device retains the last latched address. in single phase address latching mode, the alelo cycle maybe skipped and the device retains the last latched address. for 16 and 8-bit modes, consecutive address cycles mu st be within the same dwor d until the dword is com- pletely accessed (with the register exceptions noted above). although byt es and words can be accessed in any order, the diagrams in this section depi ct accessing the lower address byte or word first. note: in 8 and 16-bit modes, the alelo cycle is normally not skipped si nce sequential bytes or words are accessed in order to satisfy a comp lete dword cycle. however, there are registers for which a single byte or word access is allowed, in which case mu ltiple accesses to these registers may be performed without the need to re-latch the repeated address. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 81 lan9250 9.4.4.1 dual phase address latching the figures in this section detail read and write operations in multiplexed addressing mode with dual phase address latching for 16 and 8-bit modes. 16-bit read the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a read on ad[15:0] follows. the cycle is repeated for the other 16-bits of the dword. 16-bit read with suppressed alehi the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a read on ad[15:0] follows. the lower address is th en updated to access the opposite word. figure 9-3: multiplexed addressing with dual phase latching - 16-bit read figure 9-4: multiplexed addressing with dual phase latching - 16-bit read without alehi alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional address+1 low address high data 31:24 data 23:16 optional ad[15:8] ad[7:0] alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional address+1 low data 31:24 data 23:16 optional ad[15:8] ad[7:0] downloaded from: http:///
lan9250 ds00001913a-page 82 ? 2015 microchip technology inc. 16-bit write the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a write on ad[15:0] follows. the cycle is repeated for the other 16-bits of the dword. 16-bit write with suppressed alehi the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a write on ad[15:0] follows. the lower address is th en updated to access the opposite word. figure 9-5: multiplexed addressing with dual phase latching - 16-bit write figure 9-6: multiplexed addressing with dual phase latching - 16-bit write without alehi alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional address+1 low address high data 31:24 data 23:16 optional ad[15:8] ad[7:0] alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional address+1 low data 31:24 data 23:16 optional ad[15:8] ad[7:0] downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 83 lan9250 16-bit reads and writes to constant address the address is latched sequentially from ad[7:0] . ad[15:8] is not used or driven for the address phase. a mix of reads and writes on ad[15:0] follows. 8-bit read the address is latched sequentially from ad[7:0] . a read on ad[7:0] follows. ad[15:8] pins are not used or driven. the cycle is repeated for the other bytes of the dword. note: generally, two 16-bit reads to oppo site words of the same dword are required, with at least the lower address changing using alelo . 16-bit reads and writes to the same word is a special case. figure 9-7: multiplexed addressing with dual phase latching - 16-bit reads and writes constant address figure 9-8: multiplexed addressing with dual phase latching - 8-bit reads alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional ad[15:8] ad[7:0] data 15:8 data 7:0 data 15:8 data 7:0 data 15:8 data 7:0 data 15:8 data 7:0 ad[15:8] alelo alehi cs rd wr ad[7:0] address low address high data 7:0 optional address+1 low address high data 15:8 optional address+2 low address high data 23:16 address+3 low address high data 31:24 hi-z optional optional downloaded from: http:///
lan9250 ds00001913a-page 84 ? 2015 microchip technology inc. 8-bit read with suppressed alehi the address is latched sequentially from ad[7:0] . a read on ad[7:0] follows. ad[15:8] pins are not used or driven. the lower address is then updated to access the other bytes. 8-bit write the address is latched sequentially from ad[7:0] . a write on ad[7:0] follows. ad[15:8] pins are not used or driven. the cycle is repeated for the other bytes of the dword. figure 9-9: multiplexed addressing with dual phase latching - 8-bit reads without alehi figure 9-10: multiplexed addressing with dual phase latching - 8-bit write ad[15:8] alelo alehi cs rd wr ad[7:0] address low address high data 7:0 optional address+1 low data 15:8 optional hi-z address+2 low data 23:16 optional address+3 low data 31:24 optional alelo alehi cs rd wr address low address high data 7:0 optional address+1 low address high data 15:8 optional address+2 low address high data 23:16 address+3 low address high data 31:24 hi-z optional optional ad[15:8] ad[7:0] downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 85 lan9250 8-bit write with suppressed alehi the address is latched sequentially from ad[7:0] . a write on ad[7:0] follows. ad[15:8] pins are not used or driven. the lower address is then updated to access the other bytes. 8-bit reads and writes to constant address the address is latched sequentially from ad[7:0] . a mix of reads and writes on ad[7:0] follows. ad[15:8] pins are not used or driven. figure 9-11: multiplexed addressing with dual phase latching - 8-bit write without alehi note: generally, four 8-bit reads to oppos ite bytes of the same dword are required, with at least the lower address changing using alelo . 8-bit reads and writes to the same byte is a special case. figure 9-12: multiplexed addressing with dual phase latching - 8-bit reads and writes constant address alelo alehi cs rd wr address low address high data 7:0 optional address+1 low data 15:8 optional address+2 low data 23:16 address+3 low data 31:24 hi-z ad[15:8] ad[7:0] optional optional alelo alehi cs rd wr address low address high data 7:0 optional ad[15:8] ad[7:0] data 7:0 data 7:0 data 7:0 data 7:0 hi-z downloaded from: http:///
lan9250 ds00001913a-page 86 ? 2015 microchip technology inc. 9.4.4.2 single phase address latching the figures in this section detail multiplexed addressing mode with single phase addressing for 16 and 8-bit modes of operation. 16-bit read the address is latched simultaneously from ad[7:0] and ad[15:8] . a read on ad[15:0] follows. the cycl e is repeated for the other 16-bits of the dword. 16-bit write the address is latched simultaneously from ad[7:0] and ad[15:8] . a write on ad[15:0] follows. the cycl e is repeated for the other 16-bits of the dword. figure 9-13: multiplexed addressing with single phase latchi ng - 16-bit read figure 9-14: multiplexed addressing with single phase latching - 16-bit write alelo alehi cs rd wr address low data 15:8 data 7:0 address+1 low data 31:24 data 23:16 address high address high optional optional ad[15:8] ad[7:0] alelo alehi cs rd wr address low data 15:8 data 7:0 address+1 low data 31:24 data 23:16 address high address high optional optional ad[15:8] ad[7:0] downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 87 lan9250 16-bit reads and writes to constant address the address is latched simultaneously from ad[7:0] and ad[15:8] . a mix of reads and writes on ad[15:0] follows. .8-bit read the address is latched simultaneously from ad[7:0] and ad[15:8] . a read on ad[7:0] follows. ad[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. the cycle is repeated for the other bytes of the dword. note: generally, two 16-bit reads to oppos ite words of the same dword are required. 16-bit reads and writes to the same word is a special case. figure 9-15: multipl exed addressing with single phase latching - 16-bit reads and writes constant address figure 9-16: multiplexed addressing with single phase latching - 8-bit read alelo alehi cs rd wr address low address high data 15:8 data 7:0 optional ad[15:8] ad[7:0] data 15:8 data 7:0 data 15:8 data 7:0 data 15:8 data 7:0 data 15:8 data 7:0 alelo alehi cs rd wr address low data 7:0 address+1 low data 15:8 address high address high optional optional address+2 low data 23:16 address high address+3 low data 31:24 address high optional optional ad[15:8] ad[7:0] downloaded from: http:///
lan9250 ds00001913a-page 88 ? 2015 microchip technology inc. 8-bit write the address is latched simultaneously from ad[7:0] and ad[15:8] . a write on ad[7:0] follows. ad[15:8] pins are not used or driven for the data phase as the host could potentially continue to drive the upper address on these signals. the cycle is repeated for the other bytes of the dword. 8-bit reads and writes to constant address the address is latched simultaneously from ad[7:0] and ad[15:8] . a mix of reads and writes on ad[7:0] follows. ad[15:8] pins are not used or driven for the data phase as the ho st could potentially continue to drive the upper address on these signals. figure 9-17: multiplexed addressing with single phase latching - 8-bit write note: generally, four 8-bit reads to opposite bytes of th e same dword are required. 8-bit reads and writes to the same byte is a special case. figure 9-18: multiplexed addressing with single phase latching - 8-bit reads and writes constant address alelo alehi cs rd wr address low data 7:0 address+1 low data 15:8 address high address high optional optional address+2 low data 23:16 address high address+3 low data 31:24 address high optional optional ad[15:8] ad[7:0] alelo alehi cs rd wr address low address high data 7:0 optional ad[15:8] ad[7:0] data 7:0 data 7:0 data 7:0 data 7:0 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 89 lan9250 9.4.4.3 rd_wr / enb control mode examples the figures in this section detail read and write operations utilizing the alternative rd_wr and enb signaling. the hbi read/write mode is selectable via the hbi_rw_mode_strap . 16-bit note: the examples in this section detail 16-bit mode with dual phase latching. however, the rd_wr and enb signaling can be used identically in all othe r multiplexed addressing modes of operation. the examples in this section show the enb signal active-high and the rd_wr signal low for read and high for write. the polarities of the rd_wr and enb signals are selectable via the hbi_rd_rdwr_polarity_strap , and hbi_wr_en_polarity_strap . figure 9-19: multiplexed addressing rd_w r / enb control mode example - 16- bit read figure 9-20: multiplexed addressing rd_w r / enb control mode example - 16- bit write alelo alehi cs rd_wr enb address low address high data 15:8 data 7:0 optional address+1 low address high data 31:24 data 23:16 optional ad[15:8] ad[7:0] alelo alehi cs rd_wr enb address low address high data 15:8 data 7:0 optional address+1 low address high data 31:24 data 23:16 optional ad[15:8] ad[7:0] downloaded from: http:///
lan9250 ds00001913a-page 90 ? 2015 microchip technology inc. 9.4.5 multiplexed addressing mode timing requirements the following figures and tables specify the timing requirem ents during multiplexed address / data mode. since timing requirements are similar across the mult itude of operations (e.g. dual vs. singl e phase, 8 vs. 16-bit), many timing requirements are illustrated onto the same figures and do not necessarily repres ent any particular functional operation. the following should be noted for the timing specifications in this section: the diagrams in this section depict active-high alehi / alelo , cs , rd , wr , rd_wr and enb signals. the polarities of these signals are selectable via the hbi_ale_polarity_strap , hbi_cs_polar ity_strap , hbi_rd_rdwr_po- larity_strap , and hbi_wr_en_polarity_strap , respectively. refer to section 9.3, "control line polarity," on page 74 for additional details. qualification of the alelo and/or alehi with the cs signal is selectable via the hbi_ale_qualification_strap . this is shown as a dashed line. timing requirements between alelo / alehi and cs only apply when this mode is active. in dual phase address latching mode, the alehi and alelo cycles can be in any order. alehi first is depicted in solid line. alelo first is depicted in dashed line. a read cycle maybe followed by followed by an address cycle, a write cycle or another read cycle. a write cycle maybe followed by followed by a read cycle or another write cycle. these are shown in dashed line. 9.4.5.1 read timing requirements if rd and wr signaling is used, a host read cycle begins when rd is asserted with cs active. the cycle ends when rd is de-asserted. cs maybe asserted and de-asserted along with rd but not during rd active. alternatively, if rd_wr and enb signaling is used, a host read cycle begins when enb is asserted with cs active and rd_wr indicating a read. the cycle ends when enb is de-asserted. cs maybe asserted and de-asserted along with enb but not during enb active. please refer to section 9.4.4, "multiplexed addressing mode functional timing diagrams," on page 80 for functional descriptions. figure 9-21: multiplexed addressing read cycle timing alehi ad[7:0] input alelo ad[15:8] input enb, rd ad[15:8] output ad[7:0] output wr cs t adrs t adrh t csale t alerd t rddh, t csdh t aledv t rd t rddz, t csdz t aleale t wale t rdrd t rdwr t rdale t rdale t rdcyc rd_wr t rdwrs t rdwrh t csrd t rdcs t rddv, t csdv t rdon, t cson downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 91 lan9250 note 1: dual phase addressing note 2: depends on alehi / alelo order. table 9-1: multiplexed addressing read cycle timing values symbol description min typ max units t csale cs setup to alelo , alehi active note 3 , note 2 0n s t csrd cs setup to rd or enb active 0 ns t rdcs cs hold from rd or enb inactive 0 ns t wale alelo , alehi pulse width 10 ns t adrs address setup to alelo , alehi inactive 10 ns t adrh address hold from alelo , alehi inactive 5 ns t aleale alelo inactive to alehi active alehi inactive to alelo active note 1 , note 2 0n s t alerd alelo , alehi inactive to rd or enb active note 2 5n s t rdwrs rd_wr setup to enb active note 4 5n s t rdwrh rd_wr hold from enb inactive note 4 5n s t rdon rd or enb to data buffer turn on 0 ns t rddv rd or enb active to data valid 30 ns t rddh data output hold time from rd or enb inactive 0 ns t rddz data buffer turn off time from rd or enb inactive 9 ns t cson cs to data buffer turn on 0 ns t csdv cs active to data valid 30 ns t csdh data output hold time from cs inactive 0 ns t csdz data buffer turn off time from cs inactive 9 ns t aledv alelo , alehi inactive to data valid note 2 35 ns t rd rd or enb active time 32 ns t rdcyc rd or enb cycle time 45 ns t rdale rd or enb de-assertion time befo re address phase 13 ns t rdrd rd or enb de-assertion time before next rd or enb note 5 13 ns t rdwr rd de-assertion time before next wr note 5 , note 6 13 ns downloaded from: http:///
lan9250 ds00001913a-page 92 ? 2015 microchip technology inc. note 3: alelo and/or alehi qualified with the cs . note 4: rd_wr and enb signaling. note 5: no interposed address phase. note 6: rd and wr signaling. note: timing values are with respect to an equivalent test load of 25 pf. 9.4.5.2 write timing requirements if rd and wr signaling is used, a host write cycle begins when wr is asserted with cs active. the cycle ends when wr is de-asserted. cs maybe asserted and de-asserted along with wr but not during wr active. alternatively, if rd_wr and enb signaling is used, a host write cycle begins when enb is asserted with cs active and rd_wr indicating a write. the cycle ends when enb is de-asserted. cs maybe asserted and de-asserted along with enb but not during enb active. please refer to section 9.4.4, "multiplexed addressing mode functional timing diagrams," on page 80 for functional descriptions. figure 9-22: multiplexed addr essing write cycle timing alehi ad[7:0] input alelo ad[15:8] input enb, wr rd cs t adrs t adrh t csale t alewr t wr t wale t wrwr t wrrd t wrale t wrale t wrcyc rd_wr t rdwrs t rdwrh t cswr t wrcs t ds t dh t aleale downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 93 lan9250 note 7: dual phase addressing note 8: depends on alehi / alelo order. note 9: alelo and/or alehi qualified with the cs . note 10: rd_wr and enb signaling. note 11: no interposed address phase. note 12: rd and wr signaling. table 9-2: multiplexed addressing write cycle timing values symbol description min typ max units t csale cs setup to alelo , alehi active note 9 , note 8 0n s t cswr cs setup to wr or enb active 0 ns t wrcs cs hold from wr or enb inactive 0 ns t wale alelo , alehi pulse width 10 ns t adrs address setup to alelo , alehi inactive 10 ns t adrh address hold from alelo , alehi inactive 5 ns t aleale alelo inactive to alehi active alehi inactive to alelo active note 7 , note 8 0n s t alewr alelo , alehi inactive to wr or enb active note 8 5n s t rdwrs rd_wr setup to enb active note 10 5n s t rdwrh rd_wr hold from enb inactive note 10 5n s t ds data setup to wr or enb inactive 7 ns t dh data hold from wr or enb inactive 0 ns t wr wr or enb active time 32 ns t wrcyc wr or enb cycle time 45 ns t wrale wr or enb de-assertion time before address phase 13 ns t wrwr wr or enb de-assertion time before next wr or enb note 11 13 ns t wrrd wr de-assertion time before next rd note 11 , note 12 13 ns downloaded from: http:///
lan9250 ds00001913a-page 94 ? 2015 microchip technology inc. 9.5 indexed address mode in indexed address mode, access to the internal registers and memory of the device are indirectly mapped using index and data registers. the desired internal address is written into the device at a particular offset. the value written is then used as the internal address when the associate data regi ster address is accessed. three index / data register sets are provided allowing for multi-threaded operation without the concern of one thread corrupting the index set by another thread. endianness can be configured per index / data pair. another data register is provided for access to the fifos. the host address register map is given below. in 8-bit data mode, the host address input (addr[4:0]) is a byte address. in 16-bit data mode, addr0 is not provided and the host address input (addr[4:1]) is a word address. as discussed below in section 9.5.5.2, "index re gister bypass fifo access" , the tx and rx data fifos are accessed when reading or writing at address 18h-1bh. as discussed below in section 9.5.5.3, "fif o direct select access" , when the fifosel input is active, all access is to or from the tx and rx data fifos. table 9-3: host bus interface indexed address mode register map fifosel byte address symbol register name 0 00h-03h hbi_idx_0 host bus in terface index register 0 0 04h-07h hbi_data_0 host bus interface data register 0 0 08h-0bh hbi_idx_1 host bus in terface index register 1 0 0ch-0fh hbi_data_1 host bus interface data register 1 0 10h-13h hbi_idx_2 host bus in terface index register 2 0 14h-17h hbi_data_2 host bus interface data register 2 0 18h-1bh tx_data_fifo rx_data_fifo tx data fifo rx data fifo 0 1ch-1fh hbi_cfg host bus interface configuration register 1n at x _ d a t a _ f i f o rx_data_fifo tx data fifo rx data fifo downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 95 lan9250 9.5.1 host bus interf ace index register the index registers are writable as words or as bytes, depending upon the data mode. there is no concern about dword assembly rules when writing these registers. the index registers are formatted as follows: note 13: the default may be used to help determine the endianness of the register. 9.5.2 host bus interface configuration register the hbi configuration register is used to specify the endia nness of the interface. endiane ss for each index / data pair and for fifo accesses can be individually specified. the endianness of this register is irrelevant si nce each byte is shadowed into 4 positions. the hbi configuration register is writ able as words or as bytes, depending upon the data mode. there is no concern about dword assembly rules when writing this register . the configuration register is formatted as follows: bits description type default 31:16 reserved ro - 15:0 internal address the address used when the corresponding data register is accessed. note: the internal address provided by each index register is always considered to be a byte address. r/w 1234h note 13 bits description type default 31:28 reserved ro - 27 fifo endianness shadow 3 this bit is a shadow of bit 3. r/w 0b 26 host bus interface index / data register 2 endianness shadow 3 this bit is a shadow of bit 2. r/w 0b 25 host bus interface index / data register 1 endianness shadow 3 this bit is a shadow of bit 1. r/w 0b 24 host bus interface index / data register 0 endianness shadow 3 this bit is a shadow of bit 0. r/w 0b 23:20 reserved ro - 19 fifo endianness shadow 2 this bit is a shadow of bit 3. r/w 0b 18 host bus interface index / data register 2 endianness shadow 2 this bit is a shadow of bit 2. r/w 0b 17 host bus interface index / data register 1 endianness shadow 2 this bit is a shadow of bit 1. r/w 0b 16 host bus interface index / data register 0 endianness shadow 2 this bit is a shadow of bit 0. r/w 0b 15:12 reserved ro - 11 fifo endianness shadow 1 this bit is a shadow of bit 3. r/w 0b 10 host bus interface index / data register 2 endianness shadow 1 this bit is a shadow of bit 2. r/w 0b downloaded from: http:///
lan9250 ds00001913a-page 96 ? 2015 microchip technology inc. 9 host bus interface index / data register 1 endianness shadow 1 this bit is a shadow of bit 1. r/w 0b 8 host bus interface index / data register 0 endianness shadow 1 this bit is a shadow of bit 0. r/w 0b 7:4 reserved ro - 3 fifo endianness this bit specifies the endianness of fifo accesses when they are accessed by means other than the index / data register method. 0 = little endian 1 = big endian note: in order to avoid any ambiguity with the endianness of this register, bits 3, 11, 19 and 27 are shadowed. if any of these bits are set during a write, all of the bits will be set. r/w 0b 2 host bus interface index / data register 2 endianness this bit specifies the endianness of the index and data register set 2. 0 = little endian 1 = big endian note: in order to avoid any ambiguity with the endianness of this register, bits 2, 10, 18 and 26 are shadowed. if any of these bits are set during a write, all of the bits will be set. r/w 0b 1 host bus interface index / data register 1 endianness this bit specifies the endianness of the index and data register set 1. 0 = little endian 1 = big endian note: in order to avoid any ambiguity with the endianness of this register, bits 1, 9, 17 and 25 are shadowed. if any of these bits are set during a write, all of the bits will be set. r/w 0b 0 host bus interface index / data register 0 endianness this bit specifies the endianness of the index and data register set 0. 0 = little endian 1 = big endian note: in order to avoid any ambiguity with the endianness of this register, bits 0, 8, 16 and 24 are shadowed. if any of these bits are set during a write, all of the bits will be set. r/w 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 97 lan9250 9.5.3 index and configuratio n register data access the host data bus can be 16 or 8-bits wide. the hbi index registers and the hbi configuration register are 32-bits wide and are writable as words or as bytes, depending up on the data mode. they do not have nor do they require words or bytes to dword conversion. 9.5.3.1 write cycles a write cycle occurs when cs and wr are active (or when enb is active with rd_wr i ndicating write). on the trailing edge of the write cycle (eit her wr or cs or enb going inactive), the host data is capt ured into the con- figuration register or o ne for the index registers. depending on the bus width, either a word or a byte is written. the affected word or byte is determined by the endianness of the register (specified in the host bus interface configuration register ) and the lower address inputs. individual byte (in 16-bit data mode) access is not supported. writes following initialization following device initialization, writes from the host bus are ignored until after a read cycle is performed. writes during and foll owing power management during and following any power management mode other than d0, writes from the host bu s are ignored until after a read cycle is performed. 9.5.3.2 read cycles a read cycle occurs when cs and rd are active (or when enb is active with rd_wr indicating read). the host address is used directly from the host bus. at the beginning of the read cycle, the app ropriate register is select ed and its data is driven onto the data pins. depend- ing on the bus width, either a word or a byte is read. fo r 8 or 16-bit data modes, the returned byte or word is determined by the endianness of the register (specified in the host bus interface configuration register ) and the lower host address inputs. 9.5.4 internal register data access the host data bus can be 16 or 8-bits wide while all internal registers are 32 bits wide. the host bus interface performs the conversion from words or bytes to dword, while in 8 or 16-bit data mode. two or four accesses within the same dword are required in order to perform a write or read. each data register, along with the fifo direct address access, has a separate word or byte to dword conversion. accesses may be mixed among these (and the hbi index and c onfiguration register s) without concern of data corrup- tion. 9.5.4.1 write cycles a write cycle occurs when cs and wr are active (or when enb is active wi th rd_wr indicating write). the host address from the host bus selects the contents of one of the index registers. the result of this operation is captured on the leading edge of the write cycle. the host address inputs and the fifo direct select signal from the host bus are also capt ured on the leading edge of the write cycle. these are used to increment the appropri ate write byte / word counter (for 8 or 16-bit data mode described below) as well as to select the correct dword assembly register. on the trailing edge of the write cycle (eit her wr or cs or enb going inactive), t he host data is captured into one of the data registers. depending on the bus width, either a word or a byte is captured. for 8 or 16-bit data modes, this functions as the dword assembly with the affected wo rd or byte determined by the lower host address inputs. byte swapping is also done at this point based on the endianness of the register (specified in the host bus interface configuration register ). writes following initialization following device initialization, writes from the host bus are ignored until after a read cycle is performed. note: there are separate write byte / word counters and dword assembly registers for each of the three data registers as well as for fifo access. downloaded from: http:///
lan9250 ds00001913a-page 98 ? 2015 microchip technology inc. writes during and foll owing power management during and following any power management mode other than d0, writes from the host bu s are ignored until after a read cycle is performed. 8 and 16-bit access while in 8 or 16-bit data mode, the host is required to perfo rm two or four, 16 or 8-bit writes to complete a single dword transfer. no ordering requirements exist. the host can acce ss either the low or high word or byte first, as long as the other write(s) is(are) performed to the remaining word or bytes. a write byte / word counter keeps tra ck of the number of writes. each data register has its own byte / word counter. at the trailing edge of the writ e cycle, the appropriate counter (based on the captured host address from above) is incremented. once all writes occur, a 32-bit write is performed to the inter nal register selected by the captured address from above. the data that is written is selected from on e of the three dword assembly registers based on the captured host address from above. all of the write byte / word counters are reset if the power management mode is set to anything other than d0. 9.5.4.2 read cycles a read cycle occurs when cs and rd are active (or when en b is active with rd_wr indicating read). the host address from the host bus selects the contents of one of the index regi sters. the result of this op eration is used to select the internal register to be read and also is captured on the leading edge of the read cycle. the host address inputs and the fifo direct select signal from the host bus are also capt ured on the leading edge of the read cycle. these are used to increment the appropriat e read byte / word counter (for 8 or 16-bit data mode described below). at the beginning of the read cycle, the app ropriate register is select ed and its data is driven onto the data pins. depend- ing on the bus width, either a word or a byte is read. fo r 8 or 16-bit data modes, the returned byte or word is determined by the endianness of the data register (specified in the host bus interface configuration register ) and the lower host address inputs. polling for initialization complete before device initialization, the hbi will not return valid data. to determine when the hbi is functional, first the host bus interface index register 0 s hould be polled, then the byte order test re gister (byte_test) should be polled. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. reads during and following power management during any power management mode other than d0, reads from the host bus are ignor ed. if the power management mode changes back to d0 during an active read cycle, the tail end of the read cycle is ignor ed. internal registers are not affected and the state of the hbi does not change. note: writing the same word or bytes into the same dw ord may cause undefined or undesirable operation. the hbi hardware does not protect against this operation. accessing the same internal register using two index / data register pairs may cause undefined or unde- sirable operation. the hbi hardware does not protect against this operation. mixing reads and writes into the same data register may cause undefined or un desirable operation. the hbi hardware does not prot ect against this operation. note: there are separate read byte / word counters for ea ch of the three data registers as well as for fifo access. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 99 lan9250 8 and 16-bit access for certain register accesses, the host is required to perfor m two or four consecutive 16 or 8-bit reads to complete a single dword transfer. no ordering requirements exist. the host can access either the low or high word or byte first, as long as the other read(s) is(are) performed from the remaining word or bytes. a read byte / word counter keeps track of the number of reads. each data register has its own byte / word counter. these counters are separate from the write counters above. at the trailing edge of the read cycle, the appro- priate counter (based on the captured host address from ab ove) is incremented. on the last read for the dword, an internal read is performed to update any change on read csrs. all of the read byte / word counters are reset if the power management mode is set to anything other than d0. special csr handling live bits any register bit that is updated by a h/ w event is held at the beginning of th e read cycle to preven t it from changing during the read cycle. multiple byte / word live registers in 16 or 8-bit modes some internal registers have fields or related fields that span across multiple bytes or words. for 16 and 8-bit data reads, it is possible that the value of these fields change between host read cycl es. in order to prevent reading interme- diate values, these registers are locked when the first byte or word is read and unlocked when the last byte or word is read. the registers are unlocked if the power management mode is set to anything other than d0. change on read registers and fifos fifos or change on read registers, ar e updated at the end of the read cycle. for 16 and 8-bit modes, only one internal read cycle is indicated and occurs for the last byte or word. change on read live register bits as described above, registers with live bits are held starting at the beginning of the read cycle and those that have mul- tiple bits that span across bytes or words are also locke d for 16 and 8-bit accesses. although a h/w event that occurs during the hold or lock time would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) at the end of the read cycle and the h/w event would be lost. in order to prevent this, the individual csrs defer the h/w event update until after the read or multiple reads. registers polling during reset or initialization some registers support polling during reset or device initializa tion to determine when the device is accessible. for these registers, only one read may be per formed without the need to read the ot her word or bytes. the same byte or word of the register may be re-read repeatedly. a register that is 16 or 8-bit readable or readable during rese t or device initialization, is not ed in its register description . 9.5.4.3 host endianness the device supports big and little endian host byte ordering based upon the endianness bits in the host bus interface configuration register . when the appropriate endianness bit is low, host access is little endian and when high, host access is big endian. endianness is specified for each index / data pair and for fifo direct select accesses. all internal busses are 32-bit with little endian byte orderi ng. logic within the host bus interface re-orders bytes based on the appropriate endianness bit, and the state of the least significant address lines (addr[1:0]). note: reading the same word or bytes from the same dword may cause undefined or undesirable opera- tion. the hbi hardware does not pr otect against this operation. the hbi simply counts that four bytes have been read. accessing the same internal register using two index / data register pairs may cause undefined or unde- sirable operation. the hbi hardware does not protect against this operation. mixing reads and writes into the same data regist er may cause undefined or un desirable operation. the hbi hardware does not prot ect against this operation. downloaded from: http:///
lan9250 ds00001913a-page 100 ? 2015 microchip technology inc. data path operations for the supported endian configurations and data bus sizes are illustrated in figure 9-23: little endian ordering on page 100 and figure 9-24: big endian ordering on page 101 . figure 9-23: little endian ordering 8-bit little endian 0 1 2 3 0 1 2 3 0 7 0 78 15 16 23 31 24 a = 2 a = 3 msb lsb host data bus internal order a = 0 a = 1 16-bit little endian 0 1 2 3 0 1 2 3 0 78 15 0 78 15 16 23 31 24 a = 0 a = 1 msb lsb host data bus internal order downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 101 lan9250 figure 9-24: big endian ordering 8-bit big endian 0 1 2 3 0 78 15 16 23 31 24 3 2 1 0 0 7 a = 2 a = 3 msb lsb host data bus internal order a = 1 a = 0 16-bit big endian 0 1 2 3 0 78 15 16 23 31 24 3 2 1 0 0 78 15 a = 0 a = 1 msb lsb host data bus internal order downloaded from: http:///
lan9250 ds00001913a-page 102 ? 2015 microchip technology inc. 9.5.5 tx and rx fifo access 9.5.5.1 tx and rx status fifo peek address access normal read access to the tx or rx status fifo causes the fifo to advance to its next entry. for access to the tx and rx status fifo peek addresses, fifo does not advance to its next entry. 9.5.5.2 index register bypass fifo access in addition to the indexed access, th e index registers can be bypassed and th e fifos accessed at address 18h-1bh. at this address, host write operations ar e to the tx data fifo and host read operations are from the rx data fifo . there is no associated index register. index register bypass and fifo direct select accesse s share the same read and write byte / word counters and the same write dword assembly registers. the endianness of fifo accesses using this method is specified by the fifo endianness bit in the host bus interface configuration register . 9.5.5.3 fifo direct select access in addition to t he indexed access, a fifo direct se lect signal is provi ded. this allows the host system to access the tx and rx data fifos as if they were a large flat address space. when the fifosel input is active, all host write opera- tions are to the tx data fifo and all host read operations are from the rx data fifo. the lower host address signals are decoded in order to select the proper byte or word and to delimit dwords during a burst access. burst access is supported when reading the rx data fifo. with the fifosel input active, cs and rd (or enb with rd_wr indicating read) may be left active while the lower address lines toggle. each change of the lower address bits provides the next word or byte of data. the hbi performs an internal fifo pop (read cycl e) when it detects that a dword boundary has been crossed ( a[2] has toggled). the endianness of fifo direct select accesses is specified by the fifo endianness bit in the host bus interface con- figuration register . 9.5.6 indexed address mode fu nctional timing diagrams the following timing diagrams il lustrate example indexed ( non-multiplexed) addressing mode read and write cycles for various configurations and bus sizes. these diagrams do not cover every supported ho st bus permutation, but are selected to detail the main configuration differences (bus size, configuration/index/data/f ifo-direct cycles) within the indexed addressing mode of operation. the following should be noted for the timing diagrams in this section: the diagrams in this section depict active-high cs , rd , and wr signals. the polarities of these signals are select- able via the hbi_cs_polarity_strap , hbi_rd_rdwr_polarity_strap , and hbi_wr_en_polarity_strap , respectively. refer to section 9.3, "control line polarity," on page 74 for additional details. the diagrams in this section depict little endian byte or dering. however, configurable big and little endianess are supported via the endianness bits in the host bus interface configuration register . endianess changes only the order of the bytes involved, and not the overall timing requirements. refer to section 9.5.4.3, "host endianness," on page 99 for additional information. the diagrams in this section utilize rd and wr signals. alternative rd_wr and enb signaling is also supported, similar to the multiplexed example in section 9.4.4.3, "rd_wr / enb control mode examples" . the hbi read/ write mode is selectable via the hbi_rw_mode_strap . the polarities of the rd_wr and enb signals are select- able via the hbi_rd_rdwr_polarity_strap , and hbi_wr_en_polarity_strap . when accessing internal registers or fifos in 16 and 8- bit modes, consecutive address cycles must be within the same dword until the dword is comple tely accessed (some internal regist ers are excluded from this require- ment). although bytes and words can be accessed in any order, the diagrams in this section depict accessing the lower address byte or word first. 9.5.6.1 configuration register data access the figures in this section detail config uration register read and wr ite operations in indexed address mode for 16 and 8- bit modes. 16-bit read and write downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 103 lan9250 for writes, the address is set to access the lower word of the configuration register and fifosel is held low. data on d[15:0] is written on the trailing edge of wr . the cycle repeats for the upper word of the configuration register, if desired by the host. for reads, the address is set to access the lowe r word of the configuration register and fifosel is held low. read data is driven on d[15:0] during rd active. the cycle repeats for the upper word of the configuration register, if desired by the host. 8-bit read and write for writes, the address is set to access the lower byte of t he configuration register and fifosel is held low. data on d[7:0] is written on the trailing edge of wr . d[15:8] pins are not used or driven. th e cycle repeats for the remaining bytes of the configuration regi ster, if desired by the host. figure 9-25: indexed addressing configurat ion register access - 16-bit write/ read cs rd wr config,1'b0 data 15:8 d[15:8] a[4:1] config,1'b1 data 31:24 data 7:0 d[7:0] data 23:16 fifosel config,1'b0 data 15:8 data 7:0 config,1'b1 data 31:24 data 23:26 downloaded from: http:///
lan9250 ds00001913a-page 104 ? 2015 microchip technology inc. for reads, the address is set to access the lo wer byte of the configuration register and fifosel is held low. read data is driven on d[7:0] during rd active. d[15:8] pins are not used or driven. the cycle repeats for the remaining bytes of the configuration register, if desired by the host. 9.5.6.2 index register data access the figures in this section detail index register read and write operations in indexed address mode for 16 and 8-bit modes. 16-bit read and write for writes, the address is set to access the lower word of one of th e index registers and fifosel is held low. data on d[15:0] is written on the trailing edge of wr . the cycle repeats for the upper word of the index register, if desired by the host. for reads, the address is set to access the lower word of one of t he index registers and fifosel is held low. read data is driven on d[15:0] during rd active. the cycle repeats for the upper wo rd of the index register, if desired by the host. figure 9-26: indexed addressing configu ration register access - 8-bit write/ read note: the upper word of index registers is reserved and d ont care. therefore reads and writes to that word are not useful. cs rd wr config,2'b00 d[15:8] a[4:0] config,2'b01 data 7:0 d[7:0] data 15:8 fifosel config,2'b00 config,2'b01 config,2'b10 config,2'b11 data 23:16 data 31:24 hi-z data 7:0 data 15:8 data 23:16 data 31:24 config,2'b10 config,2'b11 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 105 lan9250 8-bit read and write for writes, the address is set to access the lower byte of one of the index registers and fifosel is held low. data on d[7:0] is written on the trailing edge of wr . d[15:8] pins are not used or driven. th e cycle repeats for the remaining bytes of the index register , if desired by the host. for reads, the address is set to access the lower byte of one of the index registers and fifosel is held low. read data is driven on d[7:0] during rd active. d[15:8] pins are not used or driven. the cycle repeats for the remaining bytes of the index register, if desired by the host. figure 9-27: indexed addressing index register access - 16-bit write/read note: the upper word of index r egisters is reserved and dont care. t herefore reads and writes to those bytes are not useful. figure 9-28: indexed addressing index register access - 8-bit write/read cs rd wr index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx fifosel index,1'b0 index 15:8 index 7:0 index,1'b1 8'hxx 8'hxx cs rd wr index,2'b00 d[15:8] a[4:0] index,2'b01 index 7:0 d[7:0] index 15:8 fifosel index,2'b00 index,2'b01 index,2'b10 index,2'b11 8'hxx 8'hxx hi-z index 7:0 index 15:8 8'hxx 8'hxx index,2'b10 index,2'b11 downloaded from: http:///
lan9250 ds00001913a-page 106 ? 2015 microchip technology inc. 9.5.6.3 internal register data access the figures in this sect ion detail typical internal register data read and write cycl es in indexed address mode for 16 and 8-bit modes. this includes an index register write followed by either a data read or write. 16-bit read one of the index registers is set as described above. the address is then set to access the lower word of the corre- sponding data register and fifosel is held low. read data is driven on d[15:0] during rd active. the cycle repeats for the upper word of the data register. figure 9-29: indexed addressing internal register data access - 16-bit read cs rd wr index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx fifosel data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 107 lan9250 16-bit write one of the index registers is set as described above. the address is then set to access the corresponding data reg- ister and fifosel is held low. data on d[15:0] is written on the trailing edge of wr . the cycle repeats for the upper word of the data register. 16-bit reads and writes to constant internal address one of the index registers is set as descri bed above. a mix of reads and writes on d[15:0] follows, with each read or write consisting of an access to both the lower and upper words of the corresponding data register. figure 9-30: indexed addressing internal register data access - 16-bit write figure 9-31: indexed addressing internal register data access - 16-bit reads/ writes constant address cs rd wr index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx fifosel data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 cs rd wr index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx fifosel data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 data,1'b0 data 15:8 data 7:0 data,1'b1 data 31:24 data 23:16 downloaded from: http:///
lan9250 ds00001913a-page 108 ? 2015 microchip technology inc. 8-bit read one of the index registers is set as described above. t he address is then set to access the lower byte of the corre- sponding data register and fifosel is held low. read data is driven on d[7:0] during rd active. d[15:8] pins are not used or driven. the cycle repeats for the remaining bytes of the data register. figure 9-32: indexed addressing internal register data access - 8-bit read cs rd wr index,2'b00 d[15:8] a[4:0] index,2'b01 index 7:0 d[7:0] index 15:8 fifosel data,2'b00 data,2'b01 index,2'b10 index,2'b11 8'hxx 8'hxx hi-z data 7:0 data 15:8 data 23:16 data 31:24 data,2'b10 data,2'b11 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 109 lan9250 8-bit write one of the index registers is set as described above. the address is then set to access the corresponding data reg- ister and fifosel is held low. data on d[7:0] is written on the trailing edge of wr . d[15:8] pins are not used or driven. the cycle repeats for the remaining bytes of the data register. figure 9-33: indexed addressing internal register data access - 8-bit write cs rd wr index,2'b00 d[15:8] a[4:0] index,2'b01 index 7:0 d[7:0] index 15:8 fifosel data,2'b00 data,2'b01 index,2'b10 index,2'b11 8'hxx 8'hxx hi-z data 7:0 data 15:8 data 23:16 data 31:24 data,2'b10 data,2'b11 downloaded from: http:///
lan9250 ds00001913a-page 110 ? 2015 microchip technology inc. 8-bit reads and writes to constant internal address one of the index registers is set as descr ibed above. a mix of reads and writes on d[7:0] follows, with each read or write consisting of an access to all four bytes of the corresponding data register. figure 9-34: indexed addressing internal register data access - 8-bit reads/ writes constant address cs rd wr index,2'b00 index 15:8 d[15:8] a[4:0] index,2'b01 index 7:0 d[7:0] fifosel data,2'b00 data 7:0 data,2'b01 data 15:8 data,2'b10 data 23:16 data,2'b00 data 7:0 data,2'b01 data 15:8 data,2'b10 data 23:16 hi-z 8'hxx index,2'b10 8'hxx index,2'b11 data,2'b10 data 23:16 data,2'b11 data 31:24 cs rd wr d[15:8] a[4:0] d[7:0] fifosel data,2'b10 data 23:16 data,2'b11 data 31:24 data,2'b00 data 7:0 data,2'b01 data 15:8 data,2'b10 data 23:16 data,2'b10 data 23:16 data,2'b11 data 31:24 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 111 lan9250 9.5.6.4 fifo direct select access the figures in this section detail fifo direct select ( fifosel ) read and write cycles in indexed address mode for 16 and 8-bit modes. additionally, fifo direct select burst reads are shown for 16, and 8-bit modes. fifo direct select burst mode supports up to 8 dwords of consecutive reads. fifo direct select ( fifosel ) read and write cycles do not required an index register write. 16-bit read fifosel is set high and address bit 1 is set to access the lower word of the fifo, while address bits 4:2 are dont care. read data is driven on d[15:0] during rd active. the cycle repeats for the upper word of the fifo. 16-bit write fifosel is set high and address bit 1 is set to access the lo wer word of the fifo, while address bits 4:2 are dont care. data on d[15:0] is written on the trailing edge of wr . the cycle repeats for the upper word of the fifo. figure 9-35: indexed addressing fifo direct select access - 16-bit read figure 9-36: indexed addressing fifo direct select access - 16-bit write cs rd wr 3'bxxx,1'b0 rx fifo 15:8 d[15:8] a[4:1] 3'bxxx,1'b1 rx fifo 31:24 rx fifo 7:0 d[7:0] rx fifo 23:16 fifosel cs rd wr 3'bxxx,1'b0 tx fifo 15:8 d[15:8] a[4:1] 3'bxxx,1'b1 tx fifo 31:24 tx fifo 7:0 d[7:0] tx fifo 23:16 fifosel downloaded from: http:///
lan9250 ds00001913a-page 112 ? 2015 microchip technology inc. 16-bit burst read fifosel is set high and address bit 1 is set to access the lower word of the fifo, while address bits 4:2 start at 0. read data is driven on d[15:0] during rd active. address bit 1 is then set to access the word of the fifo as rd is held active. while rd is held active, address bits 4:2 are cycled from 0 th rough 7 to access the 8 dwords as address bit 1 is tog- gled to access each word. fresh data is supplied each time a[1] toggles. the fifo is popped when a[2] toggles. 8-bit read fifosel is set high and address bits 1 and 0 are set to access the lower byte of the fifo, while address bits 4:2 are dont care. read data is driven on d[7:0] during rd active. d[15:8] pins are not used or dr iven. the cycle repeats for the remaining 3 bytes of the fifos dword. figure 9-37: indexed addressing fifo di rect select access - 16-bit burst read figure 9-38: indexed addressing fifo direct select access - 8-bit read cs rd wr 3'b000,1'b0 rx fifo 15:8 d[15:8] a[4:1] rx fifo 31:24 rx fifo 7:0 d[7:0] rx fifo 23:16 fifosel 3'b000,1'b1 3'b001,1'b0 3'b111,1'b0 3'b111,1'b1 3'b001,1'b1 rx fifo 15:8 rx fifo 31:24 rx fifo 7:0 rx fifo 23:16 rx fifo 15:8 rx fifo 31:24 rx fifo 7:0 rx fifo 23:16 cs rd wr 3'bxxx,2'b00 d[15:8] a[4:0] 3'bxxx,2'b01 rx fifo 7:0 d[7:0] rx fifo 15:8 fifosel 3'bxxx,2'b10 3'bxxx,2'b11 rx fifo 23:16 rx fifo 31:24 hi-z downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 113 lan9250 8-bit write fifosel is set high and address bits 1 and 0 are set to access the lower byte of the fifo, while address bits 4:2 are dont care. data on d[7:0] is written on the trailing edge of wr . d[15:8] pins are not used or driven. the cycle repeats for the remaining 3 bytes of the fifos dword. 8-bit burst read fifosel is set high and address bits 1 and 0 are set to access the lower byte of the fifo, while address bits 4:2 start at 0. read data is driven on d[7:0] during rd active. d[15:8] pins are not used or driven. address bits 1 & 0 are then cycled from 0 through 3 to access the next 3 bytes of the fifo as rd is held active. while rd is held active, address bits 4:2 are cycled from 0 through 7 to access the 8 dwords as address bits 1 & 0 are cycled from 0 through 3 to access each byte. fresh data is supplied each time a[0] toggles. the fifo is popped when a[2] toggles. figure 9-39: indexed addressing fifo direct select access - 8-bit write figure 9-40: indexed addressing fifo direct select access - 8-bit burst read cs rd wr 3'bxxx,2'b00 d[15:8] a[4:0] 3'bxxx,2'b01 tx fifo 7:0 d[7:0] tx fifo 15:8 fifosel 3'bxxx,2'b10 3'bxxx,2'b11 tx fifo 23:16 tx fifo 31:24 hi-z cs rd wr 3'b000,2'b00 d[15:8] a[4:0] rx fifo 7:0 d[7:0] rx fifo 15:8 fifosel rx fifo 23:16 rx fifo 31:24 hi-z 3'b000,2'b01 3'b000,2'b10 3'b000,2'b11 rx fifo 7:0 rx fifo 15:8 rx fifo 23:16 rx fifo 31:24 3'b111,2'b00 3'b111,2'b01 3'b111,2'b10 3'b111,2'b11 downloaded from: http:///
lan9250 ds00001913a-page 114 ? 2015 microchip technology inc. 9.5.6.5 rd_wr / enb control mode examples the figures in this section detail read and write operations utilizing the alternative rd_wr and enb signaling. the hbi read/write mode is selectable via the hbi_rw_mode_strap . 16-bit note: the examples in this section detail 16-bit mode with access to an index register. however, the rd_wr and enb signaling can be used identically for all other accesses including fifo direct select access. the examples in this section show the enb signal active-high and the rd_wr signal low for read and high for write. the polarities of the rd_wr and enb signals are selectable via the hbi_rd_rdwr_polarity_strap , and hbi_wr_en_polarity_strap . figure 9-41: indexed addressing rd_wr / enb control mode example - 16-bit write/read cs index,1'b0 index 15:8 d[15:8] a[4:1] index,1'b1 8'hxx index 7:0 d[7:0] 8'hxx fifosel index,1'b0 index 15:8 index 7:0 index,1'b1 8'hxx 8'hxx rd_wr enb downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 115 lan9250 9.5.7 indexed addressing mo de timing requirements the following figures and tables specify the timing requirements during indexed address mode. since timing require- ments are similar across the multitude of operations (e.g. 8 vs. 16-bit, index vs. configuration vs. da ta registers, fifo direct select), many timing requirements are illustrated in the same figures and do not necessarily represent any par- ticular functional operation. the following should be noted for the timing specifications in this section: the diagrams in this section depict active-high cs , rd , wr , rd_wr and enb signals. the polarities of these sig- nals are selectable via the hbi_cs_polarity_strap , hbi_rd_rdwr_polarity_strap , and hbi_wr_en_polarity_strap , respectively. refer to section 9.3, "control line polarity," on page 74 for additional details. a read cycle maybe followed by followed by a write cycle or another read cycle. a wr ite cycle maybe followed by followed by a read cycle or another write cycle. these are shown in dashed line. 9.5.7.1 read timing requirements if rd and wr signaling is used, a host read cycle begins when rd is asserted with cs active. the cycle ends when rd is de-asserted. cs maybe asserted and de-asserted along with rd but not during rd active. alternatively, if rd_wr and enb signaling is used, a host read cycle begins when enb is asserted with cs active and rd_wr indicating a read. the cycle ends when enb is de-asserted. cs maybe asserted and de-asserted along with enb but not during enb active. please refer to section 9.5.6, "indexed address mode functional timing diagrams," on page 102 for functional descrip- tions. figure 9-42: indexed addressing read cycle timing t rddv, t csdv fifosel a[4:0] enb, rd d[15:8] d[7:0] wr cs t rdon, t cson t rddh, t csdh t adv, t fdv t rd t rddz, t csdz t rdrd t rdwr t rdcyc rd_wr t rdwrs t rdwrh t csrd t rdcs t ah t ah t as t as downloaded from: http:///
lan9250 ds00001913a-page 116 ? 2015 microchip technology inc. note 14: rd_wr and enb signaling. note 15: rd and wr signaling. note: timing values are with respect to an equivalent test load of 25 pf. table 9-4: indexed addressing read cycle timing values symbol description min typ max units t csrd cs setup to rd or enb active 0 ns t rdcs cs hold from rd or enb inactive 0 ns t as address, fifosel setup to rd or enb active 0 ns t ah address, fifosel hold from to rd or enb inactive 0 ns t rdwrs rd_wr setup to enb active note 14 5n s t rdwrh rd_wr hold from enb inactive note 14 5n s t rdon rd or enb to data buffer turn on 0 ns t rddv rd or enb active to data valid 30 ns t rddh data output hold time from rd or enb inactive 0 ns t rddz data buffer turn off time from rd or enb inactive 9 ns t cson cs to data buffer turn on 0 ns t csdv cs active to data valid 30 ns t csdh data output hold time from cs inactive 0 ns t csdz data buffer turn off time from cs inactive 9 ns t fdv fifosel to data valid 30 ns t adv address to data valid 30 ns t rd rd or enb active time 32 ns t rdcyc rd or enb cycle time 45 ns t rdrd rd or enb de-assertion time before next rd or enb 13 ns t rdwr rd de-assertion time before next wr note 15 13 ns downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 117 lan9250 9.5.7.2 fifo direct select burst timing requirements if rd and wr signaling is used, a host burst read from the fifo begins when rd is asserted with cs active and fifo- sel high. as the address changes, the next data is read. the cycle ends when rd is de-asserted. cs maybe asserted and de-asserted along with rd but not during rd active. alternatively, if rd_wr and enb signaling is used, a host burst read from the fifo begins when enb is asserted with cs active, rd_wr indicating a read and fifosel high. as the address changes, th e next data is read. the cycle ends when enb is de-asserted. cs maybe asserted and de-asserted along with enb but not during enb active. please refer to section 9.5.6, "indexed address mode functional timing diagrams," on page 102 for functional descrip- tions. figure 9-43: indexed addressing fifo direct select burst read cycle timing table 9-5: indexed addressing fifo di rect select burst read cycle timing values symbol description min typ max units t csrd cs setup to rd or enb active 0 ns t rdcs cs hold from rd or enb inactive 0 ns t as address, fifosel setup to rd or enb active 0 ns t ah address, fifosel hold from to rd or enb inactive 0 ns t rdwrs rd_wr setup to enb active note 16 5n s t rdwrh rd_wr hold from enb inactive note 16 5n s t rdon rd or enb to data buffer turn on 0 ns t rddv rd or enb active to data valid 30 ns t rddh data output hold time from rd or enb inactive 0 ns t rddz data buffer turn off time from rd or enb inactive 9 ns fifosel a[4:0] enb, rd d[15:8] d[7:0] wr cs t rddh, t csdh t fdv t rddz, t csdz t rdrd t rdwr rd_wr t rdwrs t rdwrh t csrd t rdcs t as t ah t as t ah t acyc t adv t acyc t adv t adv t rddv, t csdv t rdon, t cson downloaded from: http:///
lan9250 ds00001913a-page 118 ? 2015 microchip technology inc. note 16: rd_wr and enb signaling. note 17: rd and wr signaling. note: timing values are with respect to an equivalent test load of 25 pf. t cson cs to data buffer turn on 0 ns t csdv cs active to data valid 30 ns t csdh data output hold time from cs inactive 0 ns t csdz data buffer turn off time from cs inactive 9 ns t fdv fifosel to data valid 30 ns t adv address change to next data valid 40 ns t acyc address cycle time 45 ns t rdrd rd or enb de-assertion time before next rd or enb 13 ns t rdwr rd de-assertion time before next wr note 17 13 ns table 9-5: indexed addressing fifo direct select burst read cycle timing values (continued) symbol description min typ max units downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 119 lan9250 9.5.7.3 write timing requirements if rd and wr signaling is used, a host write cycle begins when wr is asserted with cs active. the cycle ends when wr is de-asserted. cs maybe asserted and de-asserted along with wr but not during wr active. alternatively, if rd_wr and enb signaling is used, a host write cycle begins when enb is asserted with cs active and rd_wr indicating a write. the cycle ends when enb is de-asserted. cs maybe asserted and de-asserted along with enb but not during enb active. please refer to section 9.5.6, "indexed address mode functional timing diagrams," on page 102 for functional descrip- tions. figure 9-44: indexed addressing write cycle timing table 9-6: indexed addressing write cycle timing values symbol description min typ max units t cswr cs setup to wr or enb active 0 ns t wrcs cs hold from wr or enb inactive 0 ns t as address, fifosel setup to wr or enb active 0 ns t ah address, fifosel hold from to wr or enb inactive 0 ns t rdwrs rd_wr setup to enb active note 18 5n s t rdwrh rd_wr hold from enb inactive note 18 5n s t ds data setup to wr or enb inactive 7 ns t dh data hold from wr or enb inactive 0 ns enb, wr d[7:0] rd cs t wr t wrwr t wrrd t wrcyc rd_wr t rdwrh t cswr t wrcs t ds t dh d[15:8] fifosel a[4:0] t as t ah t as t ah t rdwrs downloaded from: http:///
lan9250 ds00001913a-page 120 ? 2015 microchip technology inc. note 18: rd_wr and enb signaling. note 19: rd and wr signaling. t wr wr or enb active time 32 ns t wrcyc wr or enb cycle time 45 ns t wrwr wr or enb de-assertion time before next wr or enb 13 ns t wrrd wr de-assertion time before next rd note 19 13 ns table 9-6: indexed addressing write cycle timing values (continued) symbol description min typ max units downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 121 lan9250 10.0 spi/sqi slave 10.1 functional overview the spi/sqi slave module provides a lo w pin count synchronous slave interfac e that facilitates communication between the device and a host system. the spi/sqi slave allows access to the system csrs and in ternal fifos and memories. it supports single and multiple register read and write commands with incrementing, decr ementing and static address- ing. single, dual and quad bit lanes are supported in spi mode with a clock rate of up to 80 mhz. sqi mode always uses four bit lanes and also operates at up to 80 mhz. the following is an overview of the f unctions provided by the spi/sqi slave: serial read: 4-wire (clock, select, data in and data out) re ads at up to 30 mhz. serial command, address and data. single and multiple regist er reads with incrementing, decrementing or static addressing. fast read: 4-wire (clock, select, data in and data out) reads at up to 80 mhz. serial command, address and data. dummy byte(s) for first access. single and multiple regist er reads with incrementing, decrementing or static addressing. dual / quad output read: 4 or 6-wire (clock, select, data in / out) re ads at up to 80 mhz. serial command and address, parallel data. dummy by te(s) for first access. single and multiple register reads with incrementing, decre- menting or static addressing. dual / quad i/o read: 4 or 6-wire (clock, select, data in / out) reads at up to 80 mhz. serial command, parallel address and data. dummy byte(s) for first access. single and multiple register reads with incrementing, decre- menting or static addressing. sqi read: 6-wire (clock, select, data in / out) writes at up to 80 mhz. parallel command, address and data. dummy byte(s) for first access. single and multiple regist er reads with incrementing, decrementing or static addressing. write: 4-wire (clock, select, data in and data out) writes at up to 80 mhz. serial co mmand, address and data. sin- gle and multiple register writes with incr ementing, decrementing or static addressing. dual / quad data write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 mhz. serial command and address, parallel data. single and multiple register wr ites with incrementing, decre menting or static addressing. dual / quad address / data write: 4 or 6-wire (clock, select, data in / out) writes at up to 80 mhz. serial com- mand, parallel address and data. single and multiple regi ster writes with incrementi ng, decrementing or static addressing. sqi write: 6-wire (clock, select, data in / out) writes at up to 80 mhz. parallel command, address and data. single and multiple register writes with increm enting, decrementing or static addressing. 10.2 spi/sqi slave operation input data on the sio[3:0] pins is sampled on the rising edge of the sck input clock. output data is sourced on the sio[3:0] pins with the falling edge of the clock. the sck input clock can be either an active high pulse or an active low pulse. when the scs# chip select input is high, the sio[3:0] inputs are ignored and the sio[3:0] outputs are three- stated. in spi mode, the 8-bit instruction is started on the first rising edge of the input clock after scs# goes active. the instruc- tion is always input serially on si / sio0 . for read and write instructions, two address bytes follow the in struction byte. depending on the instruction, the address bytes are input either serially, or 2 or 4 bits per clock. although all registers are accessed as dwords, the address field is considered a byte address. fourteen address bits specify the address. bits 15 and 14 of the address field specifies that the address is auto-decremented (10b) or auto-incremented (01b) for continuous accesses. for some read instructions, dummy byte cycles follow the address bytes. the device does not drive the outputs during the dummy byte cycles. the dummy byte(s) are inpu t either serially, or 2 or 4 bits per clock. for read and write instructions, one or mo re 32-bit data fields follow the dummy bytes (if present, else they follow the address bytes). the data is input either serially, or 2 or 4 bits per clock. sqi mode is entered from spi with the enable quad i/o (eqio) instruction. once in sqi mode, all further command, addresses, dummy bytes and data bytes are 4 bits per clock. sqi mode can be exited using the reset quad i/o (rstqio) instruction. downloaded from: http:///
lan9250 ds00001913a-page 122 ? 2015 microchip technology inc. all instructions, addresses and data are tr ansferred with the most-significant bit (msb) or di-bit (msd) or nibble (msn) first. addresses are transferred with the most-significant by te (msb) first. data is trans ferred with the least-significant byte (lsb) first (little endian). the spi interface supports up to a 80 mhz input clock. norma l (non-high speed) reads inst ructions are limited to 30 mhz. the spi interface supports a minimum time of 50 ns between successive commands (a minimum scs# inactive time of 50 ns). the instructions supported in spi mode are listed in table 10-1 . sqi instructions are listed in table 10-2 . unsupported instructions are must not be used. note 1: the bit width format is: command bit width, address / dummy bit width, data bit width. table 10-1: spi instructions instruction description bit width note 1 inst. code addr. bytes dummy bytes data bytes max freq. configuration eqio enable sqi 1-0-0 38h 0 0 0 80 mhz rstqio reset sqi 1-0-0 ffh 0 0 0 80 mhz read read read 1-1-1 03h 2 0 4 to ? 30 mhz fastread read at higher speed 1-1-1 0bh 2 1 4 to ? 80 mhz sdor spi dual output read 1-1-2 3bh 2 1 4 to ? 80 mhz sdior spi dual i/o read 1-2-2 bbh 2 2 4 to ? 80 mhz sqor spi quad out- put read 1-1-4 6bh 2 1 4 to ? 80 mhz sqior spi quad i/o read 1-4-4 ebh 2 4 4 to ? 80 mhz write write write 1-1-1 02h 2 0 4 to ? 80 mhz sddw spi dual data write 1-1-2 32h 2 0 4 to ? 80 mhz sdadw spi dual address / data write 1-2-2 b2h 2 0 4 to ? 80 mhz sqdw spi quad data write 1-1-4 62h 2 0 4 to ? 80 mhz sqadw spi quad address / data write 1-4-4 e2h 2 0 4 to ? 80 mhz downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 123 lan9250 note 2: the bit width format is: command bit width, address / dummy bit width, data bit width. 10.2.1 device initialization until the device has been initialized to the point where the various configuration inputs are valid, the spi/sqi interface does not respond to and is not affected by any external pin activity. once device initialization completes, the spi/sqi interface will ignore the pins until a rising edge of scs# is detected. 10.2.1.1 spi/sqi slave read po lling for initialization complete before device initialization, the spi/sqi interface will not return valid data. to determine when the spi/sqi interface is functional, the byte order test register (byte_test) should be polled. once the corre ct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. 10.2.2 access during and following power management during any power management mode other than d0, reads an d writes are ignored and t he spi/sqi interface does not respond to and is not affected by any external pin activity. once the power management mode changes back to d0, the sp i/sqi interface will ignore the pins until a rising edge of scs# is detected. to determine when the spi/sqi interface is functional, the byte order test register (byte_test) should be polled. once the correct pattern is read, the interface can be considered functional. at this point, the device ready (ready) bit in the hardware configuration register (hw_cfg) can be polled to determine when the device is fully configured. 10.2.3 spi configuration commands 10.2.3.1 enable sqi the enable sqi instruction changes the mode of op eration to sqi. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not su pported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit eqio instruction, 38h , is input into the si / sio[0] pin one bit per clock. the scs# input is brought inacti ve to conclude the cycle. table 10-2: sqi instructions instruction description bit width note 2 inst. code addr. bytes dummy bytes data bytes max freq. configuration rstqio reset sqi 4-0-0 ffh 0 0 0 80 mhz read fastread read at higher speed 4-4-4 0bh 2 3 4 to ? 80 mhz write write write 4-4-4 02h 2 0 4 to ? 80 mhz note: the host should only use single register reads (one data cycle per scs# low) while polling the byte_test register. note: the host should only use single register reads (one data cycle per scs# low) while polling the byte_test register. downloaded from: http:///
lan9250 ds00001913a-page 124 ? 2015 microchip technology inc. figure 10-1 illustrates the en able sqi instruction. 10.2.3.2 reset sqi the reset sqi instruction changes the mode of operation to spi. this instruction is supported in spi and sqi bus pro- tocols with clock frequencies up to 80 mhz . the spi/sqi slave interface is selected by first bringing scs# active. the 8-bit rstqio instruction, ffh , is input into the si / sio[0] pin, one bit per clock, in spi mode and into the sio[3:0] pins, four bits per clock, in sqi mode. the scs# input is brought inactive to conclude the cycle. figure 10-2 illustrates the reset sqi instruction for spi mode. figure 10-3 illustrates the reset sqi instruction for sqi mode. figure 10-1: enable sqi figure 10-2: spi mode reset sqi spi enable sqi sck (active high) si 0011 0 x instruction 0 so 10 z sck (active low) scs# x 1 2 3 4 5 6 7 8 x 1 2 3 4 5 6 7 8 x x x spi mode reset sqi sck (active high) si 1111 1 x instruction 1 so 11 z sck (active low) scs# x 1 2 3 4 5 6 7 8 x 1 2 3 4 5 6 7 8 x x x downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 125 lan9250 10.2.4 spi read commands various read commands are support by the spi/sqi slave. the following applies to all read commands. multiple reads additional reads, beyond the first, are performed by continuing the clock pulses while scs# is active. the upper two bits of the address specify auto-increment ing (address[15:14]=01b) or auto-decrementing (address[15:14]=10b). the inter- nal dword address is incremented, decremented, or main tained based on these bits. maintaining a fixed internal address is useful for register polling. special csr handling live bits since data is read serially, the selected registers value is saved at the beginning of each 32-bit read to prevent the host from reading an intermediate value. the saving o ccurs multiple times in a multiple read sequence. change on read registers and fifos any register that is affected by a read operation (e.g. a clear on read bit or fifo) is updated once the current data output shift has started. in the event th at 32-bits are not read when the scs# is returned high, the regi ster is still affected and any prior data is lost. change on read live register bits as described above, the current value from a register with live bits (as is the case of any register) is saved before the data is shifted out. although a h/ w event that occurs following the data captur e would still update the live bit(s), the live bit(s) will be affected (cleared, etc.) once the output shift has started and the h/w event would be lost. in order to prevent this, the individual csrs defer the h/w ev ent update until after the read indication. 10.2.4.1 read the read instruction inputs the instruction code and address bytes one bit per clock and outputs the data one bit per clock. this instruction is sup ported in spi bus protocol only with clock frequencies up to 30 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit read instruction, 03h , is input into the si / sio[0] pin, followed by the two address bytes. the addr ess bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last address bit, the so / sio[1] pin is driven starting with the msb of the lsb of the selected regist er. the remaining register bits are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the so / sio[1] pin is three-stated at this time. figure 10-3: sqi mode reset sqi sqi mode reset sqi sck (active high) sio[3:0] ff x sck (active low) scs# x 1 2 x 1 2 x x x inst downloaded from: http:///
lan9250 ds00001913a-page 126 ? 2015 microchip technology inc. figure 10-4 illustrates a typical single and multiple register read. 10.2.4.2 fast read the read at higher speed instruction inputs the instruction code and the address and dummy bytes one bit per clock and outputs the data one bit per clock. in sqi mode, t he instruction code and the address and dummy bytes are input four bits per clock and the data is output four bits per clo ck. this instruction is supported in spi and sqi bus protocols with clock frequencies up to 80 mhz . the spi/sqi slave interface is selected by first bringing scs# active. for spi mode, the 8-bit fastread instruction, 0bh , is input into the si / sio[0] pin, followed by the two address bytes and 1 dummy byte. for sqi mode, the 8-bit fas- tread instruction is input into the sio[3:0] pins, followed by the two address bytes and 3 dummy bytes. the address bytes specify a byte address within the device. on the falling clock edge following the rising edg e of the last dummy bit (or nibble), the so / sio[1] pin is driven starting with the msb of the lsb of the selected register. for sqi mode, sio[3:0] are driven starting with the msn of the lsb of the selected register. the remaining register bits are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the so / sio[3:0] pins are three-stated at this time. figure 10-4: spi read spi read single register sck (active high) si 0000 1 x instruction 1 address x so de c data a 13 ... ... x ... spi read multiple registers 00 d 7 d 6 d 5 z z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 53 54 55 56 x x 53 54 55 56 d 26 d 24 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) si 0000 1 x instruction 1 address x so de c a 13 ... x ... 00 z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... d 7 d 6 d 5 d 26 d 24 ... d 7 d 6 d 5 d 26 d 24 z x x ... ... d 25 d 25 d 25 data 1... data m data m+1... data n ... downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 127 lan9250 figure 10-5 illustrates a typical single and multip le register fast read for spi mode. figure 10-6 illustrates a typical single and multiple register fast read for sqi mode. figure 10-5: spi fast read figure 10-6: sqi fast read spi fast read single register sck (active high) si 0000 1 x instruction 1 address x so de c data a 13 ... ... x ... spi fast read multiple registers 10 d 7 d 6 d 5 z z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 61 62 63 64 x x 61 62 63 64 d 26 d 24 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) si x instruction address x so de c a 13 ... x ... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... d 7 d 6 d 5 d 26 d 24 ... d 7 d 6 d 5 d 26 d 24 z x x ... ... x x x x x x x x 25 26 27 28 29 30 31 32 25 26 27 28 29 30 31 32 dummy x x x x x x x x dummy 25 26 27 28 29 30 31 25 26 27 28 29 30 31 32 32 33 34 35 33 34 35 0000 1 1 10 d 25 d 25 d 25 data 1... data m data m+1... data n ... sqi fast read single register sck (active high) sio[3:0] x inst address h1 data h 0 sqi fast read multiple registers h 0 l0 h 1 x sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x l2 l3 l1 l0 17 18 19 20 17 18 19 20 sck (active high) x ... sck (active low) scs# ... x x x x ... ... x ... data 1... data m data n x x x x x x dummy sio[3:0] 0 b l1 h 2 h 3 inst address h1 h 0 h 0 l0 h 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 l1 l0 x x x x x x dummy 0 b 15 data m+1... l2 l3 h 3 h 0 l0 h 1 l2 l3 h 3 ... downloaded from: http:///
lan9250 ds00001913a-page 128 ? 2015 microchip technology inc. 10.2.4.3 dual output read the spi dual output read instruction inputs the instruction code and the address and dummy bytes one bit per clock and outputs the data two bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not su pported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sdor instruction, 3bh , is input into the sio[0] pin, followed by the two address bytes and 1 dummy byte. the address bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last dummy di-bit, the sio[1:0] pins are driven starting with the msbs of the lsb of the selected register. the remaining regist er di-bits are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the sio[1:0] pins are three-stated at this time. figure 10-7 illustrates a typical single and mu ltiple register dual output read. figure 10-7: spi dual output read spi dual output read single register sck (active high) sio0 0011 1 x instruction 1 address sio1 de c data a 13 ... ...... spi dual output read multiple registers 10 d 7 d 6 d 5 z z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 45 46 47 48 x x 45 46 47 48 d 29 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction address sio1 de c a 13 ...... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... ... ... x x x x x x x x 25 26 27 28 29 30 31 32 25 26 27 28 29 30 31 32 dummy x x x x x x x x dummy 25 26 27 28 29 30 31 25 26 27 28 29 30 31 32 32 33 34 35 33 34 35 0011 1 1 10 d 25 data 1... data m data m+1... data n ... d 4 d 3 d 2 d 24 d 28 d 26 d 27 x data d 7 d 6 d 5 d 4 d 3 d 2 d 29 d 25 d 24 d 28 d 26 d 27 d 7 d 6 d 5 d 4 d 3 d 2 z x d 29 d 25 d 24 d 28 d 26 d 27 x data 1... data m data m+1... data n downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 129 lan9250 10.2.5 quad output read the spi quad output read instruction inputs the instruction code a nd the address and dummy bytes one bit per clock and outputs the data four bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not su pported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sqor instruction, 6bh , is input into the sio[0] pin, followed by the two address bytes and 1 dummy byte. the address bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last dummy bit, the sio[3:0] pins are driven starting with the msn of the lsb of the selected register. the remaining register nibbles are shifted out. the scs# input is brought inactive to conclude the cycle. the sio[3:0] pins are three-stated at this time. figure 10-8 illustrates a typical single and mu ltiple register quad output read. figure 10-8: spi quad output read spi quad output read single register sck (active high) sio0 011 1 x instruction 1 address sio1 de c data a 13 spi quad output read multiple registers 10 d 5 d 4 d 1 z z x sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 37 38 39 40 x x 37 38 39 40 d 17 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction address sio1 de c a 13 ...... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... ... ... x x x x x x x x 25 26 27 28 29 30 31 32 25 26 27 28 29 30 31 32 dummy x x x x x x x x dummy 25 26 27 28 29 30 31 25 26 27 28 29 30 31 32 32 33 34 35 33 34 35 d 25 data 1... data m data m+1... data n ... d 0 d 13 d 12 d 24 d 16 d 28 d 29 x data d 5 d 4 d 1 d 0 d 13 d 12 d 17 d 25 d 24 d 16 d 28 d 29 z x x data 1... data m data m+1... data n sio2 z ... ... data 1... data m data m+1... data n d 6 d 2 d 14 d 18 d 26 d 30 z x sio3 z ... ... data 1... data m data m+1... data n d 7 d 3 d 15 d 19 d 27 d 31 z x d 5 d 4 d 1 d 0 d 13 d 12 d 6 d 2 d 14 d 7 d 3 d 15 d 17 d 25 d 24 d 16 d 28 d 29 d 18 d 26 d 30 d 19 d 27 d 31 sio2 z d 6 d 2 d 14 d 18 d 26 d 30 sio3 z d 7 d 3 d 15 d 19 d 27 d 31 z x z x 0 011 1 1 10 0 data data 36 36 d 9 d 8 d 21 d 20 d 10 d 22 d 11 d 23 downloaded from: http:///
lan9250 ds00001913a-page 130 ? 2015 microchip technology inc. 10.2.5.1 dual i/o read the spi dual i/o read instruction inputs the instruction code one bi t per clock and the address and dummy bytes two bits per clock and outputs the data two bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sdior instruction, bbh , is input into the sio[0] pin, followed by the two address bytes and 2 dummy bytes into the sio[1:0] pins. the address bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last dummy di-bit, the sio[1:0] pins are driven starting with the msbs of the lsb of the selected register. the remaining regist er di-bits are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the sio[1:0] pins are three-stated at this time. figure 10-9 illustrates a typical single and mu ltiple register dual i/o read. figure 10-9: spi dual i/o read spi dual i/o read single register sck (active high) sio0 1 x instruction 1 address sio1 de c data a 13 ... ...... spi dual i/o read multiple registers 10 d 7 d 6 d 5 z z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 37 38 39 40 x x 37 38 39 40 d 29 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction sio1 ...... sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... ... ... x x x x x x x x 25 26 27 25 26 27 dummy x 25 26 27 25 26 27 d 25 data 1... data m data m+1... data n ... d 4 d 3 d 2 d 24 d 28 d 26 d 27 x data d 7 d 6 d 5 d 4 d 3 d 2 d 29 d 25 d 24 d 28 d 26 d 27 d 7 d 6 d 5 d 4 d 3 d 2 z x d 29 d 25 d 24 d 28 d 26 d 27 x data 1... data m data m+1... data n x x x x x x x x 11 10 11 10 11 10 address de c a 13 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 z x x x x x x x x dummy x x x x x x x address dummy address dummy downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 131 lan9250 10.2.5.2 quad i/o read the spi quad i/o read instruction inputs the instruction code one bit per clock and the address and dummy bytes four bits per clock and outputs the data four bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sqior instruction, ebh , is input into the sio[0] pin, followed by the two address bytes and 4 dummy bytes into the sio[3:0] pins. the address bytes specify a byte address within the device. on the falling clock edge following the rising edge of the last dummy nibble, the sio[3:0] pins are driven starting with the msn of the lsb of the se lected register. the remaining register nibble s are shifted out on subsequent falling clock edges. the scs# input is brought inactive to conclude the cycle. the sio[3:0] pins are three-stated at this time. figure 10-10 illustrates a typical single and multiple register quad i/o read. figure 10-10: spi quad i/o read spi quad i/o read single register sck (active high) sio0 111 1 x instruction 1 sio1 data spi quad i/o read multiple registers 10 d 5 d 4 d 1 z x sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 28 x x 25 26 27 28 d 17 17 18 19 20 21 22 23 17 18 19 20 21 22 23 sck (active high) sio0 x instruction address sio1 de c a 13 ...... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 17 18 19 20 21 22 23 ... ... ... ... x x x x x x x x dummy d 25 data 1... data m data m+1... data n ... d 0 d 13 d 12 d 24 d 16 d 28 d 29 x data d 5 d 4 d 1 d 0 d 13 d 12 d 17 d 25 d 24 d 16 d 28 d 29 z x x data 1... data m data m+1... data n sio2 z ... ... data 1... data m data m+1... data n d 6 d 2 d 14 d 18 d 26 d 30 z x sio3 z ... ... data 1... data m data m+1... data n d 7 d 3 d 15 d 19 d 27 d 31 z x d 5 d 4 d 1 d 0 d 13 d 12 d 6 d 2 d 14 d 7 d 3 d 15 d 17 d 25 d 24 d 16 d 28 d 29 d 18 d 26 d 30 d 19 d 27 d 31 sio2 d 6 d 2 d 14 d 18 d 26 d 30 sio3 d 7 d 3 d 15 d 19 d 27 d 31 z x z x 0 111 1 1 10 0 x x x x x x x x dummy x x x x x x x x dummy x x x x x x x x dummy address de c a 13 z in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 z z x x x x x x x x dummy x x x x x x x x dummy x x x x x x x x dummy x x x x x x x x dummy 24 24 d 9 d 8 d 21 d 20 d 10 d 22 d 11 d 23 downloaded from: http:///
lan9250 ds00001913a-page 132 ? 2015 microchip technology inc. 10.2.6 spi write commands multiple write commands are support by the spi/sqi slave. the following applies to all write commands. multiple writes multiple reads are performed by continuing the clock pulses and input data while scs# is active. the upper two bits of the address specify auto-incrementing (a ddress[15:14]=01b) or auto-decrementing (address[15:14]=10b). the internal dword address is incremented, de cremented, or maintained based on these bits. maintaining a fixed internal address may be useful for register bit-b anging or other repeated writes. 10.2.6.1 write the write instruction inputs the instruction code and address and data bytes one bit per clock. in sqi mode, the instruc- tion code and the address and data bytes are input four bits per clock. this instruction is supported in spi and sqi bus protocols with clock frequencies up to 80 mhz . the spi/sqi slave interface is selected by first bringing scs# active. for spi mode, the 8-bit write instruction, 02h , is input into the si / sio[0] pin, followed by the two address bytes. for sqi mode, the 8-bit write instruction, 02h , is input into the sio[3:0] pins, followed by the two address bytes. the address bytes specify a byte address within the device. the data follows the address bytes. for spi mode, the data is input into the si / sio[0] pin starting with the msb of the lsb. for sqi mode the data is input nibble wide using sio[3:0] starting with the msn of the lsb. the remaining bits/ nibbles are shifted in on subsequent clock edges. the data write to the register occurs after the 32-bits are input. in the event that 32-bits are not written when the scs# is returned high, the write is cons idered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-11 illustrates a typical single and multiple register write for spi mode. figure 10-12 illustrates a typical single and multiple register write for sqi mode. figure 10-11: spi write spi write single register sck (active high) si 0000 x instruction 1 address so de c data a 13 ... ... spi write multiple registers 00 d 7 d 6 d 5 z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 53 54 55 56 x x 53 54 55 56 d 26 d 24 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) si 0000 x instruction address so de c a 13 ... 00 z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... d 7 d 6 d 5 d 26 d 24 ... d 7 d 6 d 5 d 26 d 24 x ... d 25 d 25 d 25 data 1... data m data m+1... data n ... 0 1 0 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 133 lan9250 figure 10-12: sqi write sqi write single register sck (active high) sio[3:0] x inst address h1 data h 0 sqi write multiple registers h 0 l0 h 1 x sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 x x l2 l3 l1 l0 sck (active high) x ... sck (active low) scs# ... x x x x ... ... x ... data 1... data m data n sio[3:0] 0 2 l1 h 2 h 3 inst address h1 h 0 h 0 l0 h 1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 l1 l0 0 2 data m+1... l2 l3 h 3 h 0 l0 h 1 l2 l3 h 3 ... downloaded from: http:///
lan9250 ds00001913a-page 134 ? 2015 microchip technology inc. 10.2.6.2 dual data write the spi dual data write instruction inputs the instruction code and address bytes one bit per clock and inputs the data two bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sddw instruction, 32h , is input into the sio[0] pin, followed by the two address bytes. the address bytes specify a byte address within the device. the data follows the address bytes. the data is input into the sio[1:0] pins starting with the msbs of the lsb. the remaining di-bits are shifted in on subsequent clock edges. t he data write to the register occurs after the 32-bits are input. in the event that 32-bi ts are not written when the scs# is returned high, the write is considered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-13 illustrates a typical single and multiple register dual data write. figure 10-13: spi dual data write spi dual data write single register sck (active high) sio0 0011 x instruction 1 address sio1 de c data a 13 ... ... spi dual data write multiple registers 00 z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 37 38 39 40 x x 37 38 39 40 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction address sio1 de c a 13 ... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... ... data 1... data m data m+1... data n ... 0 1 0 data ... d 7 d 6 d 5 z x d 29 d 25 d 4 d 3 d 2 d 24 d 28 d 26 d 27 x 0011 00 ... ... data 1... data m data m+1... data n d 7 d 5 d 3 d 29 d 25 d 27 d 7 d 5 d 3 z x d 29 d 25 d 27 d 6 d 4 d 2 d 24 d 28 d 26 d 6 d 4 d 2 d 24 d 28 d 26 x downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 135 lan9250 10.2.6.3 quad data write the spi quad data write instruction inputs the instruction code and address bytes one bit per clock and inputs the data four bits per clock. this instruction is supported in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sqdw instruction, 62h , is input into the sio[0] pin, followed by the two address bytes. the address bytes specify a byte address within the device. the data follows the address bytes. the data is input into the sio[3:0] pins starting with the msn of the lsb. the remain- ing nibbles are shifted in on subsequent clock edges. the data write to the register occurs after the 32-bits are input. in the event that 32-bits ar e not written when the scs# is returned high, the write is considered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-14 illustrates a typical single and multiple register quad data write. figure 10-14: spi quad data write spi quad data write single register sck (active high) sio0 00 11 x instruction 1 address sio1 de c a 13 spi quad data write multiple registers 00 z sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 sck (active high) sio0 x instruction address sio1 de c a 13 ... z sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 x x in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 17 18 19 20 21 22 23 24 17 18 19 20 21 22 23 24 ... ... 0 data d 5 d 4 d 1 z x d 17 d 25 d 0 d 13 d 12 d 24 d 16 d 28 d 29 x data d 6 d 2 d 14 d 18 d 26 d 30 d 7 d 3 d 15 d 19 d 27 d 31 z x z x data data d 9 d 8 d 21 d 20 d 10 d 22 d 11 d 23 sio2 z sio3 z 28 29 30 31 32 28 29 30 31 32 ... ... ... ... data 1... data m data m+1... data n d 5 d 4 d 1 d 0 d 13 d 12 d 17 d 25 d 24 d 16 d 28 d 29 z x x data 1... data m data m+1... data n ... ... data 1... data m data m+1... data n d 6 d 2 d 14 d 18 d 26 d 30 z x ... ... data 1... data m data m+1... data n d 7 d 3 d 15 d 19 d 27 d 31 z x d 5 d 4 d 1 d 0 d 13 d 12 d 6 d 2 d 14 d 7 d 3 d 15 d 17 d 25 d 24 d 16 d 28 d 29 d 18 d 26 d 30 d 19 d 27 d 31 sio2 z sio3 z 00 11 1 00 0 downloaded from: http:///
lan9250 ds00001913a-page 136 ? 2015 microchip technology inc. 10.2.6.4 dual address / data write the spi dual address / data write instruction inputs the instruction code one bit per clock and the address and data bytes two bits per clock. this instruction is support ed in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sdadw instruction, b2h , is input into the sio[0] pin, followed by the two address bytes into the sio[1:0] pins. the address bytes specify a byte address within the device. the data follows the address bytes. the data is input into the sio[1:0] pins starting with the msbs of the lsb. the remaining di-bits are shifted in on subsequent clock edges. t he data write to the register occurs after the 32-bits are input. in the event that 32-bi ts are not written when the scs# is returned high, the write is considered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-15 illustrates a typical single and multiple register dual address / data write. figure 10-15: spi dual address / data write spi dual address / data write single register sck (active high) sio0 011 x instruction 1 sio1 data ... ... spi dual address / data write multiple registers 00 z x sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 30 31 32 x x 29 30 31 32 17 18 19 17 18 19 sck (active high) sio0 x instruction sio1 ... sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x 17 18 19 17 18 19 ... ... ... data 1... data m data m+1... data n ... 0 data ... d 7 d 6 d 5 z x d 29 d 25 d 4 d 3 d 2 d 24 d 28 d 26 d 27 x ... ... data 1... data m data m+1... data n d 7 d 5 d 3 d 29 d 25 d 27 d 7 d 5 d 3 z x d 29 d 25 d 27 d 6 d 4 d 2 d 24 d 28 d 26 d 6 d 4 d 2 d 24 d 28 d 26 x 1 address de c a 13 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address z address de c a 13 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address 011 1 00 0 1 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 137 lan9250 10.2.6.5 quad address / data write the spi quad address / data write instruction inputs the instruction code one bit per clock and the address and data bytes four bits per clock. this instruction is suppor ted in spi bus protocol only with clock frequencies up to 80 mhz . this instruction is not supported in sqi bus protocol. the spi slave interface is selected by first bringing scs# active. the 8-bit sqadw instruction, e2h , is input into the sio[0] pin, followed by the two address bytes into the sio[3:0] pins. the address bytes specify a byte address within the device. the data follows the address bytes. the data is input into the sio[3:0] pins starting with the msn of the lsb. the remain- ing nibbles are shifted in on subsequent clock edges. the data write to the register occurs after the 32-bits are input. in the event that 32-bits ar e not written when the scs# is returned high, the write is considered invalid and the register is not affected. the scs# input is brought inactive to conclude the cycle. figure 10-16 illustrates a typical single and multiple register dual address / data write. 10.3 tx and rx fifo access 10.3.0.1 tx and rx status fifo peek address access normal read access to the tx or rx status fifo causes the fifo to advance to its next entry. for access to the tx and rx status fifo peek addr esses, the fifo does not ad vance to its next entry. figure 10-16: spi qu ad address / data write spi quad address / data write single register sck (active high) sio0 0 11 x instruction 1 sio1 spi quad address / data write multiple registers 00 sck (active low) scs# x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x 17 18 19 20 17 18 19 20 sck (active high) sio0 x instruction sio1 ... sck (active low) scs# ... x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x x ... ... 0 data d 5 d 4 d 1 z x d 17 d 25 d 0 d 13 d 12 d 24 d 16 d 28 d 29 x data d 6 d 2 d 14 d 18 d 26 d 30 d 7 d 3 d 15 d 19 d 27 d 31 z x z x data data d 9 d 8 d 21 d 20 d 10 d 22 d 11 d 23 sio2 sio3 ... ... ... ... data 1... data m data m+1... data n d 5 d 4 d 1 d 0 d 13 d 12 d 17 d 25 d 24 d 16 d 28 d 29 z x x data 1... data m data m+1... data n ... ... data 1... data m data m+1... data n d 6 d 2 d 14 d 18 d 26 d 30 z x ... ... data 1... data m data m+1... data n d 7 d 3 d 15 d 19 d 27 d 31 z x d 5 d 4 d 1 d 0 d 13 d 12 d 6 d 2 d 14 d 7 d 3 d 15 d 17 d 25 d 24 d 16 d 28 d 29 d 18 d 26 d 30 d 19 d 27 d 31 sio2 sio3 0 11 1 00 0 address de c a 13 z in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 z z address de c a 13 in c a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 z z z 11 downloaded from: http:///
lan9250 ds00001913a-page 138 ? 2015 microchip technology inc. 10.4 spi/sqi timing requirements note 3: the read instruction is limi ted to 30 mhz maximum note 4: depends on loading of 30 pf or 10 pf note 5: depending on the clock frequency and pulse width, data may not be valid until following the next rising edge of sck . the host spi controller may need to delay the sampling of the data by either a fixed time or by using the falling edge of sck . figure 10-17: spi/sqi input timing figure 10-18: spi/sqi output timing table 10-3: spi/sqi timing values symbol description min typ max units f sck sck clock frequency note 3 30 / 80 mhz t high sck high time 5.5 ns t low sck low time 5.5 ns t scss scs# setup time to sck 5n s t scsh scs# hold time from sck 5n s t scshl scs# inactive time 50 ns t su data input setup time to sck 3n s t hd data input hold time from sck 4n s t on data output turn on time from sck 0n s t v data output valid time from sck note 4 , note 5 11.0/9.0 ns t ho data output hold time from sck 0n s t dis data output disable time from scs# inactive 20 ns sck si/sio[3:0] scs# t scss t high t low t su t hd t scshl t scsh so/sio[3:0] sck t high t low scs# t dis t on t v t ho downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 139 lan9250 11.0 host mac 11.1 functional overview the host mac incorporates the essential protocol requirements for operating an ethernet/ieee 802.3-compliant node and provides an interface between the ho st and the ethernet phy. on the front end, the host mac interfaces to the host via 2 sets of fifos (tx data fifo, tx status fifo, rx data fifo, rx status fifo). an additional bus is used to access the host mac csrs via the host mac csr interface command register (mac_csr_cmd) and host mac csr interface data register (mac_csr_data) system registers. the receive and transmit fifos allow increased packet bu ffer storage to the host ma c. the fifos are a conduit between the host and the host mac through which all transm itted and received data and status information is passed. deep fifos allow a high degree of latency tolerance relative to the various transport and os software stacks reducing and minimizing overrun conditions. both the host mac and the tx/rx fifos have separate receive and transmit data paths. the host mac can store up to 250 ethernet packets utilizing fifos, totaling 16kb, with a packet granularity of 4 bytes. this memory is shared by the rx and tx blocks and is configurable in te rms of allocation via the hardware configura- tion register (hw_cfg) register to the ranges described in section 11.10.3, "fifo memory allocation configuration" . this depth of buffer st orage minimizes or eliminates receive overruns. on the back end, the host mac interfaces with the 10/100 ethernet phy via an internal smi (serial management inter- face) bus. this allows the host mac acce ss to the phys internal registers via the host mac mii access register (hmac_mii_acc) and host mac mii data register (hmac_mii_data) . the host mac interfaces to the phy via an internal mii (media independent interface) connection allo wing for incoming and outgoing ethernet packet transfers. the host mac can operate at either 100mbps or 10mbps in both half-duplex or full-duplex modes. when operating in half-duplex mode, the host mac complies fully with sect ion 4 of iso/iec 8802-3 (ansi/ieee standard) and ansi/ieee 802.3 standards. when operating in full- duplex mode, the host mac complies with ieee 802.3 full-duplex operation standard. the host mac provides programmable enhanced features desi gned to minimize host supervision, bus utilization, and pre- or post-message processing. these features include the ability to disable retries after a collision, dynamic frame check sequence (fcs) generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce min- imum frame size attributes, and automatic retransmission and detection of collision frames . the host mac can sustain transmission or reception of minimally-siz ed back-to-back packets at full line speed with an interpacket gap (ipg) of 9.6 microseconds for 10 mbps and 0.96 microseconds for 100 mbps. the primary attributes of the host mac are: transmit and receive message data encapsulation framing (frame boundary delimitation, frame synchronization) error detection (physical medium transmission errors) media access management medium allocation (collision detection, except in full-duplex operation) contention resolution (collision handli ng, except in full-duplex operation) flow control during full-duplex mode decoding of control frames (pause co mmand) and disabling the transmitter generation of control frames interface between the host bus interface and the ethernet phy. 11.2 flow control the host mac supports full-duplex flow control using the pause operation and control fram e. half-duplex flow control using back pressure is also supported. the host ma c flow control is configured via the memory mapped host mac automatic flow control configuration register (afc_cfg) located in the system csr space and the host mac flow control register (hmac_flow) located in the host mac csr space. 11.2.1 full-duplex flow control the pause operation inhibits transmission of data frames for a specified period of time. a pa use operation consists of a frame containing the globally assigned multicast address (01-80-c2-00-00-01), the pause opcode, and a parameter indicating the quantum of slot time (512 bit times) to inhibit data transmissions. the pause parameter may range from downloaded from: http:///
lan9250 ds00001913a-page 140 ? 2015 microchip technology inc. 0 to 65,535 slot times. the host mac logic, upon receiv ing a frame with the reserved multicast address and pause opcode, inhibits data frame transmissions for the length of ti me indicated. if a pause request is received while a trans- mission is in progress, then the pause will take effect afte r the transmission is complete. control frames are received, processed by the host mac, and passed on. the device will automatically transmit pause frames based on the settings of the host mac automatic flow control con- figuration register (afc_cfg) and the host mac flow control register (hmac_flow) . when the rx fifo reaches the level set in the automatic flow control high level (afc_hi) field of host mac automatic flow control configuration register (afc_cfg) , the device will transmit a pause frame. the pause time field that is transmitted is set in the pause time (fcpt) field of the host mac flow control register (hmac_flow) register. when the rx fifo drops below the level set in the automatic flow control low level (afc_lo) field of host mac automatic flow control configuration register (afc_cfg) , the device will automatically transmit a pause fram e with a pause time of zero. the device will only send another pause frame when the rx fifo level falls below automatic flow control low level (afc_lo) and then exceeds automatic flow control high level (afc_hi) again. 11.2.2 half-duplex flow control (backpressure) in half-duplex mode, backpressure is used for flow c ontrol. when the rx fifo re aches the level set in the automatic flow control high level (afc_hi) field of host mac automatic flow control configuration register (afc_cfg) , the host mac will be enabled to collide with incoming frames . the host mac transmit logi c enters a state at the end of current transmission (if any), where it waits for the be ginning of a receive frame. based on the settings in host mac automatic flow control configuration register (afc_cfg) , backpressure can be enabled on any frame, a broadcast frame, any multicast frame or frames that match the stations address decoding logic. in order to avoid any late collisions the host mac only generates collision-based backpressure at the start of a new frame. once a new receive frame starts, the host mac intentional transmits which will result in a collision. upon sensing the collision, the remote station will back off its transmission. following the transmission of the intentional collision, the host mac waits for the next receive frame. this pattern continues until either the rx fifo drops below the level set in the automatic flow control high level (afc_hi) or until the duration specified by backpressure duration (back_dur) in field of host mac automatic flow control configuration register (afc_cfg) is reached. in either case, the host mac will allow one frame to be received before returning to backpressure operation. note that the backpressure duration is timed from when the rx fifo reaches the level set in automatic flow control high level (afc_hi) , regardless when or if actual backpressure occurs. 11.3 virtual local area network (vlan) support virtual local area networks (vlans), as defined within th e ieee 802.3 standard, provi de network administrators a means of grouping nodes within a larger network into broadcast domains. to implement a vlan, four extra bytes are added to the basic ethernet packet. as shown in figure 11-1 , the four bytes are inserted after the source address field and before the type/length field. the first two bytes of the vlan tag identify the tag, and by convention are set to the value 0x8100. the last two bytes identify the specific vlan associated with the packet and provide a priority field. the device supports vlan-tagged packets and provides two host mac registers, host mac vlan1 tag register (hmac_vlan1) and host mac vlan2 tag register (hmac_vlan2) , which are used to identify vlan-tagged pack- ets. the hmac_vlan1 register is used to specify the vlan 1 tag which will increase the legal frame length from 1518 to 1522 bytes. the hmac_vlan2 register is used to spec ify the vlan2 tag which will increase the legal frame length from 1518 to 1538 bytes. if a packet arrives bearing either of these tags in the two bytes succeeding the source address downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 141 lan9250 field, the controller will recognize the packet as a vlan-tagged packet, allowing the packet to be received and pro- cessed by the host software. if both vlan1 and vlan2 tag iden tifiers are used, each should be unique. if both are set to the same value, vlan1 is given higher precedence and the maximum legal frame length is set to 1522. figure 11-1: vlan frame preamble 7 bytes sof 1 byte dest. addr. 6 bytes source addr. 6 bytes type 2 bytes data 46-1500 bytes fcs 4 bytes standard ethernet frame (1518 bytes) preamble 7 bytes sof 1 byte dest. addr. 6 bytes source addr. 6 bytes type 2 bytes data 46-1500 bytes fcs 4 bytes ethernet frame with vlan tag (1522 bytes) tpid 2 bytes type 2 bytes tpid 2 bytes vlan id 12 bits user priority 3 bits cfi 1 bit tag control information (tci) defines the vlan to which the frame belongs canonical address format indicator indicates the frames priority tag protocol id: \x81-00 downloaded from: http:///
lan9250 ds00001913a-page 142 ? 2015 microchip technology inc. 11.4 address filtering the ethernet address fields of an ethe rnet packet consist of two 6-byte fiel ds: one for the destination address and one for the source address. the first bit of the destination address signifies whether it is a physical address or a multicast address. the host mac address check logic filters the frame based on the ethernet receive filter mode that has been enabled. the various filter modes of the host mac are specif ied based on the state of the control bits in the host mac control register (hmac_cr) , as shown in table 11-1: . please refer to the section 11.15.1, "host mac control register (hmac_cr)," on page 193 for more information on this register. frames that fail the address f iltering are accepted only if the receive all mode (rxall) bit in the receive configuration register (rx_cfg) is set. the filtering fail bit in the rx status will be set for these frames. 11.4.1 perfect filtering this filtering mode passes only incoming frames whose destination address field exactly matches the value pro- grammed into the host mac address high register (hmac_addrh) and the host mac address low register (hmac_addrl) . the mac address is formed by the c oncatenation of these two registers. broadcast frames are also accepted if disable broadcast frames (bcast) is low. note: if the hmac_addrh and hmac_addrl registers are set to the broadcast address, broadcast frames will be accepted regardless of the setting of the bcast bit. table 11-1: address filtering modes mcpas prms invfilt ho hpfilt description 00000 perfect - mac address perfect fil- tering only for all addresses. broadcast frames accepted if bcast is low. 00001 hash perfect - mac address per- fect filtering for physical address and hash filtering for multicast addresses. broadcast frames accepted if bcast is low. 00011 hash only - hash filtering for physical and multicast addresses. broadcast frames accepted if bcast is low. 00100 inverse filtering x1 00x promiscuous 0x 1 1000x perfect all multicast - pass all multicast frames including broad- casts. frames with physical addresses are perfect-filtered 10011 hash only all multicast - pass all multicast frames including broad- casts. frames with physical addresses are hash-filtered downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 143 lan9250 11.4.2 hash only filtering this type of filtering checks for inco ming receive packets with either multicas t or physical destination addresses, and executes an imperfect address filtering against the hash tabl e. the hash table is formed by merging the values in the host mac multicast hash table high register (hmac_hashh) and the host mac multicast hash table low register (hmac_hashl) to form a 64-bit hash table. during imperfect hash filtering, the destination address in the incoming frame is passed through the crc logic and the upper 6-bits of the crc register are used to index the cont ents of the hash table. the most significant bit determines the register to be used (hmac_hashh or hmac_hashl), while t he other five bits determine the bit within the register. a value of 00000 selects bit 0 of the hmac_hashl regist er and a value of 11111 selects bit 31 of the hmac_hashh register. broadcast frames are also accepted if disable broadcast frames (bcast) is low. 11.4.3 hash perfect filtering in hash perfect filtering, if the received frame is a physi cal address, the host mac packet filter will perfect-filter the incoming frames destination field with the value programmed into the host mac address high register (hmac_ad- drh) and the host mac address low register (hmac_addrl) . however, if the incoming frame is a multicast frame, the host mac packet filter function performs an imperfect address filtering against the hash table. the imperfect filtering against the hash table is the same imperfect filtering process described in section 11.4.2, "hash only filtering" . broadcast frames are also accepted if disable broadcast frames (bcast) is low. note: if bit 31 of hmac_hashh is set, the broadcast addre ss will cause a hash match and broadcast frames will be accepted regardless of the setting of the bcast bit. 11.4.4 inverse filtering in inverse filtering, the host mac packe t filter accepts incoming frames with a destination address not matching the per- fect address (i.e., the value programmed into the host mac address high register (hmac_addrh) and the host mac address low register (hmac_addrl) ) and rejects frames with destination addresses matching the perfect address. note: if the hmac_addrh and hmac_addrl registers are set to the broadcast address, broadcast frames will be filtered regardless of th e setting of the bcast bit. 11.4.5 promiscuous when the promiscuous mode (prms) bit is set, all frames are accepted regardless of their destination address. note: broadcast frames will be accepted regardless of the setting of the bcast bit. 11.4.6 perfect filt ering all multicast if the received frame is a physical address, the host mac pa cket filter will perfect-filter th e incoming frames destination field with the value programmed into the host mac address high register (hmac_addrh) and the host mac address low register (hmac_addrl) . with the pass all multicast (mcpas) bit of the host mac control register (hmac_cr) set, all multicast frames are accepted. this includes all broadcast frames as well. 11.4.7 hash only filtering all multicast if the received frame is a physical address, the host mac pack et filter will execute an imperf ect address filtering against the hash table. the imperfect filterin g against the hash table is the same im perfect filtering process described in section 11.4.2, "hash only filtering" . with the pass all multicast (mcpas) bit of the host mac control register (hmac_cr) set, all multicast frames are accepted. this includes all broadcast frames as well. note: if bit 31 of hmac_hashh is set, the broadcast add ress will cause a hash match and broadcast frames will be accepted regardless of the setting of the bcast bit. downloaded from: http:///
lan9250 ds00001913a-page 144 ? 2015 microchip technology inc. 11.5 frame filtering following the address filtering, frames are acce pted or rejected according to the following: good frames that pass the address filter ing are accepted. in the rx status fo r these frames, the filtering fail bit will be clear (since the frame passed the addre ss filter). the packet filter bit will be set. good frames that fail the addre ss filtering are accepted if the receive all mode (rxall) bit in the receive config- uration register (rx_cfg) is set. in the rx status for these frames, the filtering fail bit will be set (since the frame failed the address filter). the packet filter bit will al so be set (since the rxall bit allowed the acceptance of the frame). a good broadcast frame is accepted if it passes th e address filtering or if the rxall bit is set. the disable broad- cast frames (bcast) bit in the receive configuration register (rx_cfg) determines if the packet filter bit in the rx status is set (bcast=0) or cleared (bcast=1). note that disable broadcast frames (bcast) doesnt cause the frame to be dropped if it passes the address filtering or if the rxall bit is set. the filtering fail bit will indicate if the address filtering passed or failed. a good control frame is accepted if it passes the address filtering or if th e rxall bit is set. the pass control frames (fcpass) bit in the host mac flow control register (hmac_flow) determines if the packet filter bit in the rx status is set (fcpass=1) or cleared (fcpass=0). note that pass control frames (fcpass) being low doesnt cause the frame to be dropped if it passes the address filtering or if th e rxall bit is set. the filtering fail bit will indicate if the address filtering passed or failed. a frame that has an error (runt, collision, crc, too long) and is greater than 60 bytes in length is accepted if it passes the address filtering or if the rxall bit is set. the pass bad frames (passbad) bit in the receive con- figuration register (rx_cfg) determines if the packet filt er bit in the rx status is set (passbad=1) or cleared (passbad=0). the filtering fail bit will indicate if the address filter ing passed or failed. a frame that has an error (runt, collision, crc) and is 60 bytes or under in length is accepted if it passes the address filtering or if the rxall bit is set and the pass bad frames (passbad) bit is set. the packet filter bit in the rx status is set for these frames . the filtering fail bit will indicate if the address filtering passed or failed. 11.6 wake-on-lan (wol) the following bits of the host mac wake-up control and status register (hmac_wucsr) , when enabled, may allow a wol event to be asserted: perfect da wakeup enable (pfda_en) broadcast wakeup enable (bcst_en) wake-up frame enable (wuen) magic packet enable (mpen) the wol wait for sleep (wol_wait_sleep) bit in host mac wake-up control and status register (hmac_wucsr) will delay the wol functions until the host has put the device into a power down mode. wol events may be indicated to the power management block via the wake on status (wol_sts) bit of the power management control register (pmt_ctrl) . each wol event type is detailed in the following sub-sections. the wol feature is part of the broader power management features of the device and can be used to trigger the power management event output pin ( pme ) or general interrupt request pin ( irq ). this is accomplished by enabling the desired wol feature and setting the wake-on-enable (wol_en) bit of the power management control register (pmt_ctrl) . refer to section 6.3, "power management," on page 44 for additional information. 11.6.1 perfect da detection setting the perfect da wakeup enable (pfda_en) bit in the host mac wake-up control and status register (hmac_wucsr) places the mac in the perfect da detection mode . in this mode, normal data reception is disabled, and detection logic within the mac examines the destination address of each received frame. when a frame whose destination addr ess matches that specified by the host mac address high register (hmac_ad- drh) and host mac address low register (hmac_addrl) is received, the perfect da frame received (pfda_fr) bit in the host mac wake-up control and status register (hmac_wucsr) is set. when the host clears the pfda_en bit, the host mac will resume normal receive operation. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 145 lan9250 11.6.2 broadcast detection setting the broadcast wakeup enable (bcst_en) bit in the host mac wake-up control and status register (hmac_wucsr) places the mac in the broadcast detection mode. in this mode, no rmal data reception is disabled, and detection logic within the mac examines the destination address of each received frame. when a frame whose destination address is ff ff ff ff ff ff is received, the broadcast frame received (bcast_fr) bit in the wucsr is set. when the host clears the bcst_en bit, the host mac will resume normal receive operation. 11.6.3 wake-up frame detection eight programmable wakeup frame filters are supported. each filter has a 128-bit byte mask that indicates which bytes of the frame should be compared by the mac. a crc-16 is calculated over thes e bytes. the result is then compared with the filters respective crc-16 to determine if a match exists. setting the wake-up frame enable (wuen) in the host mac wake-up control and status register (hmac_wucsr) , places the host mac in the wake-up fram e detection mode. in this mode, normal data reception is disabled, and detec- tion logic within the host mac examines received da ta for the pre-programmed wake-up frame patterns. upon detection, the remote wake-up frame received (wufr) in the host mac wake-up control and status register (hmac_wucsr) register is set. when the host clears the wuen bi t, the host mac will resume normal receive oper- ation. before putting the host mac into the wake-up frame detection state, the host must provide the detection logic with a list of sample frames and their corresponding byte ma sks. this information must be written into the host mac wake-up frame filter register (hmac_wuff) . the wake-up frame filter is configured through this register using an index mech- anism. after power-on reset, hardware reset, or soft re set, the host mac loads the first value written to the hmac_wuff register to the first dword in the wake-up frame filter (filter 0 byte mask 0). the second value written to this register is loaded to the sec ond dword in the wake-up frame filter (filter 0 byte mask 1) and so on for all 40 dwords. the wake-up frame filter functionally is described below. the host mac supports eight programmable 128-bit wake-up f ilters that support many different receive packet patterns. if remote wake-up mode is enabled, the remote wake-up fu nction receives all frames addressed to the host mac. it then checks each frame against the enabled filter and recogniz es the frame as a remote wake-up frame if it passes the wakeup frame filter registers add ress filtering and crc value match. in order to determine which bytes of the frames should be checked by the crc module, th e host mac uses a program- mable byte mask and a programmable pattern offset for each of the eight supported filters. the patterns offset defines the location of the first byte that should be che cked in the frame. since the destination address is checked by the address filtering function , the pattern offset is always greater than 12. the byte mask is a 128-bit field that specifies whether or not each of the 128 contiguous bytes within the frame, begin- ning in the pattern offset, should be che cked. if bit j in the byte mask is set, the detection lo gic checks byte offset +j in the frame. in order to load the wake-up frame filter, the host must perform 40 writes to the host mac wake-up frame filter register (hmac_wuff) . the contents of the host mac wake-up frame filter register (hmac_wuff) may be obtained by reading all 40 dwords. ta b l e 11 - 2 shows the wake-up frame fi lter registers structure. at the completion of the crc-16 checking process, the c rc-16 calculated using the patt ern offset and byte mask is compared to the expected crc-16 value associated with the filter. if a match occurs, a remote wakeup event is sig- naled. table 11-2: wakeup frame filter register structure filter 0 byte mask 0 filter 0 byte mask 1 filter 0 byte mask 2 filter 0 byte mask 3 filter 1 byte mask 0 filter 1 byte mask 1 downloaded from: http:///
lan9250 ds00001913a-page 146 ? 2015 microchip technology inc. filter 1 byte mask 2 filter 1 byte mask 3 filter 2 byte mask 0 filter 2 byte mask 1 filter 2 byte mask 2 filter 2 byte mask 3 filter 3 byte mask 0 filter 3 byte mask 1 filter 3 byte mask 2 filter 3 byte mask 3 filter 4 byte mask 0 filter 4 byte mask 1 filter 4 byte mask 2 filter 4 byte mask 3 filter 5 byte mask 0 filter 5 byte mask 1 filter 5 byte mask 2 filter 5 byte mask 3 filter 6 byte mask 0 filter 6 byte mask 1 filter 6 byte mask 2 filter 6 byte mask 3 filter 7 byte mask 0 filter 7 byte mask 1 filter 7 byte mask 2 filter 7 byte mask 3 reserved filter 3 command reserved filter 2 command reserved filter 1 command reserved filter 0 command reserved filter 7 command reserved filter 6 command reserved filter 5 command reserved filter 4 command filter 3 offset filter 2 offset filter 1offset filter 0 offset filter 7 offset filter 6 offset filter 5 offset filter 4 offset filter 1 crc-16 filter 0 crc-16 filter 3 crc-16 filter 2 crc-16 table 11-2: wakeup frame filter register structure (continued) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 147 lan9250 the filter i byte mask defines which incoming frame bytes f ilter i will examine to determin e whether or not this is a wakeup frame. ta b l e 11 - 3 , describes the byte masks bit fields. filter x mask 0 corresponds to bits [31:0]. where the lsb corresponds to the first byte on the wire. filter x mask 1 corresponds to bits [63:32]. where the lsb corresponds to the first byte on the wire. filter x mask 2 corresponds to bits [95:64]. where the lsb corresponds to the first byte on the wire. filter x mask 3 corresponds to bits [127:96]. where the lsb corresponds to the first byte on the wire. the following tables define elements common to both wuff register structures. the filter i command register controls filter i operation. ta b l e 11 - 4 shows the filter i command register. the filter i offset register defines the offset in the frames destination address field from which the frames are examined by filter i. table 11-5 describes the filter i offset bit fields. filter 5 crc-16 filter 4 crc-16 filter 7 crc-16 filter 6 crc-16 table 11-3: filter i byte mask bit definitions filter i byte mask description bits description 127:0 byte mask: if bit j of the byte mask is set, the crc machine processes byte pattern-offset + j of the incoming frame. otherwise, byte pattern-offset + j is ignored. table 11-4: filter i command bit definitions filter i commands bits description 3:2 address type: defines the destination address type of the pattern. 00 = pattern applies only to unicast frames. 10 = pattern applies only to multicast frames. x1 = pattern applies to all frames that have passed the regular receive filter. 1 reserved 0 enable filter: when bit is set, filter i is enabl ed, otherwise, filter i is disabled. table 11-2: wakeup frame filter register structure (continued) downloaded from: http:///
lan9250 ds00001913a-page 148 ? 2015 microchip technology inc. the filter i crc-16 register contains the crc-16 result of the frame that should pass filter i. table 11-6: describes the filter i crc-16 bit fields. the crc-16 is calculated as follows: at the start of a frame, crc-16 is init ialized with the value ffffh. crc-16 is updated when the pattern offset and mask indicate the received byte is part of the checksum calculation. the following algorithm is used to update the crc-16 at that time: let: ^ denote the exclusive or operator. data [7:0] be the received data byte to be included in the checksum. crc[15:0] contain the calculated crc-16 checksum. f0 f7 be intermediate results, calculated when a data byte is determined to be part of the crc-16. calculate: f0 = crc[15] ^ data[0] f1 = crc[14] ^ f0 ^ data[1] f2 = crc[13] ^ f1 ^ data[2] f3 = crc[12] ^ f2 ^ data[3] f4 = crc[11] ^ f3 ^ data[4] f5 = crc[10] ^ f4 ^ data[5] f6 = crc[09] ^ f5 ^ data[6] f7 = crc[08] ^ f6 ^ data[7] the crc-16 is updated as follows: crc[15] = crc[7] ^ f7 crc[14] = crc[6] crc[13] = crc[5] crc[12] = crc[4] crc[11] = crc[3] crc[10] = crc[2] crc[9] = crc[1] ^ f0 crc[8] = crc[0] ^ f1 crc[7] = f0 ^ f2 crc[6] = f1 ^ f3 crc[5] = f2 ^ f4 crc[4] = f3 ^ f5 crc[3] = f4 ^ f6 table 11-5: filter i offset bit definitions filter i offset description bits description 7:0 pattern offset: the offset of the first byte in the fr ame on which crc is checked for wakeup frame recognition. the mac checks the first offset byte of the frame for crc and checks to determine whether the frame is a wakeup frame. offset 0 is the first byte of the in coming frame's destination address. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 149 lan9250 crc[2] = f5 ^ f7 crc[1] = f6 crc[0] = f7 table 11-7 indicates the cases that produce a wake when the wake-up frame enable (wuen) bit of the host mac wake-up control and status register (hmac_wucsr) is set. all other cases do not generate a wake. note 1: as determined by bit 0 of filter i command. note 2: crc matches filter i crc-16 field. note 3: as determined by bit 9 of wucsr. note 4: as determined by bits 3:2 of filter i command. note 5: when wake-up frame detection is enabled via the wake-up frame enable (wuen) bit of the host mac wake-up control and status register (hmac_wucsr) , a broadcast wake-up frame will wake-up the device despite the state of the disable broadcast frames (bcast) bit in the host mac control register (hmac_cr) . note: x indicates dont care. table 11-6: filter i crc-16 bit definitions filter i crc-16 description bits description 15:0 pattern crc-16: this field contains the 16-bit crc value from the pattern and the byte mask pro- grammed to the wakeup filter register function. this value is compared against the crc calculat ed on the incoming frame, and a match indicates the reception of a wakeup frame. table 11-7: wakeup generation cases filter enabled ( note 1 ) frame type crc match ( note 2 ) global unicast enabled ( note 3 ) pass regular receive filter address type ( note 4 ) yes unicast yes yes x x yes unicast yes x yes unicast (=00) yes multicast yes x yes multicast (=10) yes broadcast ( note 5 ) y e sxxx y e sxy e sxy e sp a s s e d receive filter (=x1b) downloaded from: http:///
lan9250 ds00001913a-page 150 ? 2015 microchip technology inc. 11.6.4 magic packet detection setting the magic packet enable bit (mpen) in the host mac wake-up control and status register (hmac_wucsr) places the host mac in the magic packe t detection mode. in this mode, normal data reception is disabled, and detec- tion logic within the host mac examines received data for a magic packet. upon detection, the magic packet received bit (mpr) in the hmac_wucsr register is set. when the host clears the mpen bit, the host mac will resume normal receive operation. in magic packet mode, the host mac cons tantly monitors each frame addressed to the node for a specific magic packet pattern. only packets passing the address filtering check of section 11.4 (see note 6 ) are checked for the magic packet requirements. once the address requirement has been met, the host mac checks the re ceived frame for the pattern 48hff_ff_ff_ff_ff_ff after the destination and source addr ess field. the host mac then looks in the frame for 16 repetitions of the host mac address without any breaks or inte rruptions. in case of a break in the 16 address repetitions, the host mac again scans for the 48'hff_ff_ff_ff_ff_ff pa ttern in the incoming frame. the 16 repetitions may be anywhere in the frame but must be preceded by the synchroni zation stream. the device will also accept a multicast frame, as long as it detects the 16 duplications of the host mac address. for example, if the host mac address is 00h 11h 22h 33h 44h 55h, then the ma c scans for the following data sequence in an ethernet frame: destination address source ad dress ff ff ff ff ff ff 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 crc note 6: normally, for magic packet detection, address filtering should be set for perfect filtering or hash perfect filtering . 11.7 receive checksum offload engine (rxcoe) the receive checksum offload e ngine provides assistance to the host by calculating a 16-bit checksum for a received ethernet frame. the rxcoe readily suppo rts the following ieee802.3 frame formats: type ii ethernet frames snap encapsulated frames support for up to 2, 802.1q vlan tags the resulting checksum value can also be modified by software to support other frame formats. the rxcoe has two modes of operation. in mode 0, the rxcoe calculates the checksu m between the first 14 bytes of the ethernet frame and the fc s. this is illustrated in figure 11-2 . in mode 1, the rxcoe supports vlan tags and a snap header. in this mode, the rxcoe calculates the checksum at the start of l3 packet. the vlan1 tag register is used by th e rxcoe to indicate what protocol type is to be used to indicate the existence of a vlan t ag. this value is typically 8100h. example frame configurations: figure 11-2: rxcoe checksum calculation dst src ty p e frame data f cs calculate checksum downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 151 lan9250 figure 11-3: type ii ethernet frames figure 11-4: ethernet frame with vlan tag figure 11-5: ethernet frame with length field and snap header dst src pr o t 0 1 2 3 l3 packet f c s calculate checksum 1dword dst src 81 0 0 vi d 0 1 2 3 ty p e 4 l3 packet f c s calculate checksum 1dword dst src l3 packet fc s sn a p 0 sn a p 1 le n 0 1 2 {dsap, ssap, ctrl, oui[23:16]} {oui[15:0], pid[15:0]} 3 4 5 calculate checksum 1dword downloaded from: http:///
lan9250 ds00001913a-page 152 ? 2015 microchip technology inc. the rxcoe supports a maximum of two vlan tags. if there ar e more than two vlan tags, the vlan protocol identifier for the third tag is treated as an ethernet type field. the ch ecksum calculation will begin immediately after the type field. note that in all cases, the checksum calculation ends just be fore the frames fcs field. in the case where padding is added to meet the minimum frame length requirement, the checksum calculation will also include the pads byte(s). this may lead to unexpected results if the pad byte(s) are not zero. the rxcoe resides in the rx path within the mac. as the rxcoe receives an ethernet frame, it calculates the 16-bit checksum. the rxcoe passes the ethernet frame to the rx fifo with the checksum appended to the end of the frame. the rxcoe inserts the checksum immediately after the last by te of the ethernet frame and before it transmits the status word. the packet length field in the rx status word (refer to section 11.12.3 ) will indicate that the frame size has increased by two bytes to accommodate the checksum. note: when enabled, t he rxcoe calculates a checksum for every received frame. setting the rx checksum offload engi ne enable (rx_coe_en) bit in the host mac checksum offload engine control register (hmac_coe_cr) enables the rxcoe, while the rx checksum offload engine mode (rx_coe_mode) bit selects the operating mode. when the rxcoe is disabled, the received data is simply passed through the rxcoe unmodified. note: software applications must stop the receiver and fl ush the rx data path before changing the state of the rx checksum offload engine enable (rx_coe_en) or rx checksum offload engine mode (rx_coe_- mode) bits. figure 11-6: ethernet frame with vlan tag and snap header figure 11-7: ethernet frame with multiple vlan tags and snap header dst src 81 0 0 vi d l3 packet f c s sn a p 0 sn a p 1 3 le n 0 1 2 {dsap, ssap, ctrl, oui[23:16]} {oui[15:0], pid[15:0]} 4 5 6 calculate checksum 1dword dst src 81 0 0 vi d l3 packet fc s sn a p 0 sn a p 1 5 le n 0 1 2 {dsap, ssap, ctrl, oui[23:16]} {oui[15:0], pid[15:0]} 6 7 8 calculate checksum 81 0 0 vi d 4 1dword downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 153 lan9250 note: when the rxcoe is enabled, automatic pad stripping must be disabled ( automatic pad stripping (pad- str) bit of the host mac control register (hmac_cr) ) and vice versa. these functions cannot be enabled simultaneously. 11.7.1 rx checksum calculation the checksum is calculated 16 bits at a time. in the case of an odd sized frame, an extra byte of zero is used to pad up to 16 bits. consider the following packet: da, sa, type, b0, b1, b2 bn, fcs let [a, b] = a*256 + b; if the packet has an even number of octets then checksum = [b1, b0] + c0 + [b3, b2] + c1 + + [bn, bn-1] + cn-1 where c0, c1, ... cn-1 are the carry out results of the intermediate sums. if the packet has an odd number of octets then checksum = [b1, b0] + c0 + [b3, b2] + c1 + + [0, bn] + cn-1 11.8 transmit checksum offload engine (txcoe) the transmit checksum offload engine provides assistance to the cpu by calculating a 16- bit checksum, typically for tcp, for a transmit ethernet frame. the txcoe calculates the checksum and inserts the results back into the data stream as it is transferred to the mac. to activate the txcoe and perform a checksum calculation, the host must first set the tx checksum offload engine enable (tx_coe_en) bit in the host mac checksum offload engine control register (hmac_coe_cr) . the host then pre-pends a 3 dword buffer to the data that will be transmitted. the prepended buffer includes a tx command a, tx command b, and a 32-bit tx checksum preamble (refer to ta b l e 11 - 8 ). when the ck bit of the tx command b is set in conjunction with the fs bit of tx command a and the tx checksum offload engine enable (tx_coe_en) bit of the host mac checksum offl oad engine control r egister (hmac_coe_cr) register, the txcoe will perform a checksum calculation on the a ssociated packet. the tx checksum preambl e instructs the txco e on the handling of the associated packet. the txcssp - tx checksum start pointer field of the tx checksum preamble defi nes the byte offset at which the data checksum calculation will begin. t he checksum calculation will begin at this offset and will con- tinue until the end of the packet. the data checksum calculatio n must not begin in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet. when the calculation is complete, the checksu m will be inserted into the packet at the byte offset defined by the txcsloc - tx checksum location field of the tx checksum preamble. the tx checksum cannot be inserted in the mac head er (first 14 bytes) or in the last 4 bytes of the tx packet. if the ck bit is not set in the first tx command b of a packet, the packet is passed directly through the txcoe without modification, regardless if the txcoe_en is set. an example of a tx packet with a prepended tx checksum preamble can be found in section 11.11.6.3, "tx example 3" . in this example, the host provides the ethernet frame to the ethernet controller in four frag- ments, the first containing the tx checksum preamble. figure 11-8 shows how these fragments are loaded into the tx data fifo. for more information on the tx command a and tx command b, refer to section 11.11.2, "tx command format," on page 161 . if the tx packet already includes a partial checksum calc ulation (perhaps inserted by an upper layer protocol), this checksum can be included in the hardware checksum calculation by setting the tx cssp field in the tx checksum pre- amble to include the partial checksum. the partial checksum can be replac ed by the completed ch ecksum calculation by setting the txcsloc pointer to point to the location of the partial checksum. downloaded from: http:///
lan9250 ds00001913a-page 154 ? 2015 microchip technology inc. note: when the txcoe is enabled, the third dword of th e prepended packet is not transmitted. however, 4 bytes must be added to the packet length field in tx command b. note: software applications must stop the transmitter and fl ush the tx data path before changing the state of the txcoe_en bit. however, the ck bit of tx command b can be set or cleared on a per-packet basis. note: the txcoe_mode may only be changed if the tx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the tx ethernet path is dis abled and the tli is empty. note: the tx checksum preamble must be dword-aligned. note: tx preamble size is accounted for in both the buffer length and packet length. note: the first buffer, which contains the tx prea mble, may not contain any ethernet frame data figure 11-8 illustrates the use of a prepended checksum preamble when transmitting an ethernet frame consisting of 3 payload buffers. table 11-8: tx checksum preamble field description 31 txcsudp - tx checksum udp frame this bit specifies if a checksum result of 0x0000 should be changed to 0xffff. 30:28 reserved 27:16 txcsloc - tx checksum location this field specifies the byte offset where the tx checksum will be inserted in the tx packet. the checksum will replace two bytes of data starting at this offset. the tx checksum cannot be inserted in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet. 15:12 reserved 11:0 txcssp - tx checksum start pointer this field indicates start offset, in bytes, where the checksum calculation will begin in the associated tx packet. the data checksum calculation must not begin in the mac header (first 14 bytes) or in the last 4 bytes of the tx packet. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 155 lan9250 figure 11-8: tx example illustrating a prepended tx checksum preamble tx command 'a' pad dword 1 tx command 'a' tx command 'b' 10-byte end offset padding payload fragment 2 tx command 'a' tx command 'b' data written to the device payload fragment 3 tx command 'a' tx command 'b' tx checksum preamble note: the tx checksum preamble is pre-pended to data to be transmitted. fs is set in tx command 'a' and ck is set in tx command 'b'. no start offset may be added. fs must not be set for subsequent fragments of the same packet. tx command 'b' payload fragment 1 downloaded from: http:///
lan9250 ds00001913a-page 156 ? 2015 microchip technology inc. 11.8.1 tx checksum calculation the tx checksum calculation is performed using t he same operation as the rx checksum shown in section 11.7.1 , with the exception that the calculation starts as indicated by the tx che cksum preamble and the transmitted checksum is the ones-compliment of the calculated value. udp checksums are optional un der ipv4, and a checksum value of zero indica tes to the receiver that no checksum was calculated. under ipv6, however, according to rfc 2460, the udp checksum is not optional. a calculated checksum that yields a result of zero must be changed to ffffh for insertion into the udp header. ipv6 receivers discard udp packets containing a zero checksum. bit 31 of the checksum preamble specifies if a result of 0x0000 should be changed to 0xffff. this allows the choice of checksum usage for udp and other purposes. 11.9 host mac address the host mac address is configured via the host mac address low register (hmac_addrl) and host mac address high register (hmac_addrh) . these registers contain the 48-bit physical address of the host mac. the contents of these registers may be loaded directly by the host, or optionally, by the eeprom loader from eeprom at power-on (if a programmed eeprom is detected). table 11-9 below illustrates the byte ordering of the hmac _addrl and hmac_addrh registers with respect to the reception of the ethernet physical address. also shown is the correlation bet ween the eeprom addresses and hmac_addrl and hmac_addrh registers. for example, if the desir ed ethernet physical address is 12-34-56-78-9a-bc, the hmac_addrl and hmac_addrh registers would be programmed as shown in figure 11-9 . the values required to automatic ally load this configuration from the eeprom are also shown. note: by convention, the right nibble of the left most byte of the ethernet addr ess (in this example, the 2 of the 12h) is the most significant nibble and is transmitted/received first. table 11-9: eeprom byte orderi ng and register correlation eeprom address register locations writ ten order of recep tion on ethernet 01h hmac_addrl[7:0] 1 st 02h hmac_addrl[15:8] 2 nd 03h hmac_addrl[23:16] 3 rd 04h hmac_addrl[31:24] 4 th 05h hmac_addrh[7:0] 5 th 06h hmac_addrh[15:8] 6 th figure 11-9: example eeprom mac address setup 12h 0 7 34h 8 15 56h 16 23 78h 24 31 9ah bch xx xx a5h 12h 34h 56h 78h 9ah bch 00h 01h 02h 03h 04h 05h 06h eeprom hmac_addrh 0 78 15 16 23 24 31 hmac_addrl downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 157 lan9250 for more information on the eeprom and eepr om loader, refer to section 13.0, "i2c mast er eeprom controller," on page 282 . 11.10 fifos the device contains four host-accessible fifos (tx status, rx status, tx data, and rx data) and two internal inac- cessible host mac tx/rx mil fifo s (tx mil fifo, rx mil fifo). 11.10.1 tx/rx fifos the tx/rx data and status fifos store the incoming and ou tgoing address and data information, acting as a conduit between the host bus interface (hbi) and the host mac. the sizes of these fifos are configurable via the hardware configuration register (hw_cfg) register to the ranges described in table 11-10 . refer to section 11.10.3, "fifo memory allocation configuration" for additional information. the the rx and tx fifos related register definitions can be found in section section 11.14, "host mac & fifo interface registers" . the tx and rx data fifos have the base address of 20h and 00h respectively. however, each fifo is also accessible at seven additional contiguous memory locations, as can be seen in figure 5-1: register address map on page 30 . the host may access the tx or rx data fifos at any of these alias port locations, as they all function identically and contain the same data. this alias port addressing is impl emented to allow hosts to burst through sequential addresses. for hbi access, the tx and rx data fi fos may also be accessed using fifo direct selection mode. in this mode, the address input is ignored and all read access are directed to the rx data fifo while all write accesses are directed to the tx data fifo. see section 9.4.3.2, "fifo direct select access," on page 80 and section 9.5.5.3, "fifo direct select access," on page 102 . the tx and rx status fifos can each be read from two register locations; the status fifo port, and the status fifo peek. the tx and rx status fifo ports (48h and 40h res pectively) will perform a destructive read, popping the data from the tx or rx status fifo. the tx and rx status fi fo peek register locations (4ch and 44h respectively) allow a non-destructive read of the top (oldest) location of the fifos. proper use of the the tx/rx data and st atus fifos, including the correct data formatting is described in detail in sec- tion 11.11, "tx data path operation," on page 159 and section 11.12, "rx data path operation," on page 170 . 11.10.2 mil fifos the mac interface layer (mil), within the host mac, contains a 2kb transm it and a 128 byte receive fifo which are separate from the tx and rx fifos. these mil fifos are not directly acce ssible from the hbi. the differentiation between the tx/rx fifos and the tx/rx mil fifos is that once the transmit or receive packets are in the mil fifos, the host no longer can control or access the tx or rx da ta. the mil fifos are essentiall y the working buffers of the host mac logic. in the case of reception, the data must be moved into the rx fifos be fore the host can access the data. for tx operations, the mil oper ates in store-and-forward mode and will queue an entire frame before beginning transmission. as space in the tx mil fifo frees, da ta is moved into it from the tx data fifo. depending on the size of the frames to be transmitted, the host mac can hold up to two ethernet frames. this is in addition to any tx data that may be queued in the tx data fifo. conversely, as data is received, it is moved from the host mac to the rx mil fifo, and then into the rx data fifo. when the rx data fifo fills up, the current or subsequent rx frames will be lost until r oom is made in the rx data fifo. for each frame of data that is lost, the host mac rx dropped frames counter register (rx_drop) is incre- mented. rx and tx mil fifo levels are not visible to the host processor and operate independent of the tx/rx fifos. fifo levels set for the tx/rx data and status fifos do not take into consideration the mil fifos. 11.10.3 fifo memory allocation configuration tx and rx fifo space is configurable through the hardware configuration register (hw_cfg) . the user must select the fifo allocation by setting the tx fifo size (tx_fif_sz) field in the hardware configuration register (hw_cfg) . the tx_fif_sz field selects the total allocation for the tx da ta path, including the tx stat us fifo size. the tx status fifo size is fixed at 512 bytes (128 tx status dwords). the tx status fifo length is su btracted from the total tx fifo size with the remainder being the tx data fifo size . the minimum size of the tx fifos is 2kb (tx data and tx status fifos combined). note that tx data fifo space includes both commands and payload data. downloaded from: http:///
lan9250 ds00001913a-page 158 ? 2015 microchip technology inc. rx fifo size is the remainder of the unallocated fifo space (16384 bytes C tx fifo size). the rx status fifo size is always equal to 1/16 of the rx fifo size. the rx status fifo length is subtracted from the total rx fifo size with the remainder being the rx data fifo size. for example, if tx_fif_sz = 6 then: total tx fifo size = 6144 bytes (6kb) tx status fifo size = 512 bytes (fixed) tx data fifo size = 6144 C 512 = 5632 bytes rx fifo size = 16384 C 6144 = 10240 bytes (10kb) rx status fifo size = 10240 / 16 = 640 bytes (160 rx status dwords) rx data fifo size = 10240 C 640 = 9600 bytes table 11-10 contains an overview of the config urable tx/rx fifo sizes and defaults. table 11-11: shows every valid setting for the tx_fif_sz field and the resulting fifo sizes. no te that settings not shown in this table are reserved and should not be used. note: the rx data fifo is considered full 4 dwords before th e length that is specifie d in the hw_cfg register. table 11-10: tx/rx fifo configurable sizes fifo size range default tx status 512 512 rx status 128-892 704 tx data 1536-13824 4608 rx data 1920-13440 10560 table 11-11: valid tx/rx fifo allocations tx_fif_sz tx data fifo size (bytes) tx status fifo size (bytes) rx data fifo size (bytes) rx status fifo size (bytes) 2 1536 512 13440 896 3 2560 512 12480 832 4 3584 512 11520 768 5 4608 512 10560 704 6 5632 512 9600 640 7 6656 512 8640 576 8 7680 512 7680 512 9 8704 512 6720 448 10 9728 512 5760 384 11 10752 512 4800 320 12 11776 512 3840 256 13 12800 512 2880 192 14 13824 512 1920 128 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 159 lan9250 11.11 tx data path operation data is queued for transmission by writing it into the tx data fifo. each packet to be transmitted may be divided among multiple buffers. each buffer starts with a two dword tx command (tx command a and tx command b). the tx command instructs the device on the handling of the associ ated buffer. packet boundaries are delineated using control bits within the tx command. the host provides a 16-bit packet tag field in the tx co mmand. the packet tag value is appended to the corresponding tx status dword. all packet tag fields must have the same value for all buffers in a given packet. if tags differ between buffers in the same packet the txe error will be asserted. an y value may be chosen for a packet tag as long as all tags in the same packet are identical. packet tags also provide a method of synchronization between transmitted packets and their associated status. software can use unique packet tags to assist with validating matching status completions. note: the use of packet tags is not required by the hardware . this field can be used by the lan software driver for any application. packet tags is only one application example. the packet length field in the tx command specifies the nu mber of bytes in the associated packet. all packet length fields must have the same value for all buffers in a given packet. hardware compares the packet length field and the actual amount of data received by the ethernet controller. if the actual packet length count does not match the packet length field as defined in the tx command, th e transmitter error (txe) flag is asserted. the device can be programmed to start payload transmission of a buffer on a byte boundary by setting the data start offset field in the tx command. the data start offset field points to the actual start of the payload data within the first 8 dwords of the buffer. data before the data start offset pointer will be ignored. when a packet is split into multiple buffers, each successive buffer may begin on any arbitrary byte. the device can be programmed to strip padding from the end of a transmit packet in the event that the end of the packet does not align with the ho st burst boundary. this feature is necessary when the device is operating in a system that always performs multi-word bursts. in such cases the device mu st guarantee that it can accept data in multiples of the burst length regardless of the actual packet length. when conf igured to do so, the device will accept extra data at the end of the packet and will remove the extra padding before tr ansmitting the packet. the device automatically removes data up to the boundary specified in the buffer end alignment field specified in each tx command. the host can instruct the device to issue an interrupt when t he buffer has been fully loaded into the tx fifo contained in the device and transmitted. this feature is enabled through the tx co mmand interrupt on completion field. upon completion of transmission, irres pective of success or failure, the status of the transmission is written to the tx status fifo. tx status is available to the host and may be read using pio operations. an interrupt can be optionally enabled by the host to indicate the availabilit y of a programmable number tx status dwords. before writing the tx command and payload data to the tx fifo, the host must check the available tx fifo space by performing a pio read of the tx fifo information re gister (tx_fifo_inf) . the host must ensure that it does not over- fill the tx fifo or the tx error (txe) flag will be asserted. downloaded from: http:///
lan9250 ds00001913a-page 160 ? 2015 microchip technology inc. the host proceeds to write the tx command by first writing tx command a, then tx command b. after writing the command, the host can then move the payload data into the tx fifo. tx status dwords ar e stored in the tx status fifo to be read by the host at a later time u pon completion of the data transmission onto the wire. figure 11-10: simplified host tx flow diagram not last buffer idle check available fifo space init write buffer last buffer in packet tx status available write tx command write start padding (optional) read tx status (optional) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 161 lan9250 11.11.1 tx buffer format tx buffers exist in the hosts memory in a given format. t he host writes a tx command word into the tx data buffer before moving the ethernet packet data. the tx command a and command b are 32-bit values that are used by the device in the handling and processing of the associated et hernet packet data buffer. buffer alignment, segmentation and other packet processing parameters are included in the command structure. the buff er format is illustrated in figure 11-11 . figure 11-11 shows the tx buffer as it is written into the device. it should be noted that not all of the data shown in this diagram is actually stored in the tx data fifo. this must be taken into ac count when calculating the actual tx data fifo usage. please refer to section 11.11.5, "calculating actual tx data fifo usage" for a detailed explanation on calculating the actual tx data fifo usage. 11.11.2 tx command format the tx command instructs the tx fifo controller on handling the subsequent buffer. the command precedes the data to be transmitted. the tx command is divided into tw o, 32-bit words; tx command a and tx command b. there is a 16-bit packet tag in the tx command b command word. packet tags may, if host software desires, be unique for each packet (i.e., an incrementing count). the value of the tag will be returned in the tx status word for the associated packet. the packet tag can be used by host software to uniquely identify each status word as it is returned to the host. both tx command a and tx command b are required for each buffer in a given packet. tx command b must be identical for every buffer in a given packet. if the tx command b words do not match, the ethernet controller will assert the transmitter error (txe) flag. figure 11-11: tx buffer format tx command 'a' offset + data dword0 .. . . . last data & pad 0 31 1st 2nd 3rd last host write order optional pad dword0 .. . optional pad dwordn tx command 'b' optional offset dword0 .. . optional offset dwordn downloaded from: http:///
lan9250 ds00001913a-page 162 ? 2015 microchip technology inc. 11.11.2.1 tx command a table 11-12: tx command 'a' format bits description 31 interrupt on completion (ioc). when set, the tx_ioc bit will be asserted in the interrupt status register (int_sts) when the current buffer has been fully loaded into the tx fifo. 30:26 reserved. these bits are reserved. always write zeros to this field to guarantee future compatibility. 25:24 buffer end alignment. this field specifies the al ignment that must be maintained on the last data transfer of a buffer. the host will add extra dwords of data up to the alignment specified in the table below. the device will remove the extra dwords. this mechanism can be used to maintain cache line alignment on host processors. 23:21 reserved. these bits are reserved. always write zeros to this field to guarantee future compatibility 20:16 data start offset (bytes). this field specifies the offs et of the first byte of tx data. the offset value can be anywhere from 0 bytes to a 31 byte offset. 15:14 reserved. these bits are reserved. always write zeros to this field to guarantee future compatibility 13 first segment (fs). when set, this bit indicates that the associ ated buffer is the first segment of the packet. 12 last segment. when set, this bit indicates that the associat ed buffer is the last segment of the packet 11 reserved. these bits are reserved. always write zeros to this field to guarantee future compatibility. 10:0 buffer size (bytes). this field indicates the number of bytes contained in the buffer following this com- mand. this value, along with the buffer end alignm ent field, is read and checked by the device and used to determine how many extra dwords were added to the end of the buffer. a running count is also maintained in the device of the cumulative buffer sizes for a given packet. this cumulative value is compared against the packet length field in the tx command b word and if they do not correlate, the txe flag is set. the buffer size specified does not include the buffe r end alignment padding or data start offset added to a buffer. [25] [24] end alignment 0 0 4-byte alignment 0 1 16-byte alignment 1 0 32-byte alignment 11 r e s e r v e d downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 163 lan9250 11.11.2.2 tx command b 11.11.3 tx data format the tx data section begins at the third dword in the tx buffer (after tx command a and tx command b). the location of the first byte of valid buffer data to be transmitt ed is specified in the data start offset field of the tx com- mand a word. table 11-14, "tx data start offset" , shows the correlation between the setting of the lsbs in the data start offset field and the byte location of the first valid data byte. additionally, transmit buffer data can be offset by up to 7 additional dwords as indicated by the upper three msbs (5:2) in the data start offset field. tx data is contiguous until the end of the buffer. the buf fer may end on a byte boundary. unused bytes at the end of the packet will not be sent to the host mac interface layer for transmission. the buffer end alignment field in tx command a specifie s the alignment that must be maintained for the associated buffer. end alignment may be specified as 4-, 16-, or 32-byt e. the host processor is responsible for adding the additional data to the end of the buffer. the hardware will automatically remove this extra data. 11.11.3.1 tx buffer fragmentation rules transmit buffers must adhere to the following rules: each buffer can start and end on any arbitrary byte alignment the first buffer of any trans mit packet can be any length middle buffers (i.e., those with first segment = last segm ent = 0) must be greater than , or equal to 4 bytes in length the final buffer of any transmit packet can be any length table 11-13: tx command 'b' format bits description 31:16 packet tag. the host should write a unique packet identifier to this field. this identifier is added to the corresponding tx status word and can be used by t he host to correlate tx status words with their cor- responding packets. the use of packet tags is not required by the hardware. this field can be used by the lan software driver for any application. packet tags is one application example. 15 reserved. this bit is reserved. always write zero to this bit to guarantee future compatibility. 14 tx checksum enable (ck). when this bit is set in conjunction with the first segment (fs) bit in tx command a and the tx checksum offload engine enable (tx_coe_en) bit in the host mac checksum offload engine control register (hmac_coe_cr) , the tx checksum offload engine (txcoe) will calculate a l3 checksum for the associated frame. 13 add crc disable. when set, the automatic addit ion of the crc is disabled. 12 disable ethernet frame padding. when set, this bit prevents the aut omatic addition of padding to an ethernet frame of less than 64 bytes. the crc fiel d is also added despite the state of the add crc disable field. 11 reserved. these bits are reserved. always write zeros to this field to guarantee future compatibility. 10:0 packet length (bytes). this field indicates the total number of bytes in the current packet. this length does not include the offset or padding. if the packet length field does not match the actual number of bytes in the packet the transmitter error (txe) flag will be set. table 11-14: tx data start offset data start offset [1:0]: 11 10 01 00 first tx data byte: d[31:24] d[23:16] d[15:8] d[7:0] downloaded from: http:///
lan9250 ds00001913a-page 164 ? 2015 microchip technology inc. the mil operates in st ore-and-forward mode and has specific rules with respect to fragmented packets. the total space consumed in the tx mil fifo must be lim ited to no more than 2kb - 3 dwords (2,036 bytes total). any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a driver-supplied buffer) before the transmit packet can be sent to the device. one approach to determine whether a pack et is too fragmented is to calculate th e actual amount of space that it will consume, and check it against 2,036 byte s. another approach is to check the number of buffers against a worst-case limit of 86 (see explanation below). for the best case alignment scenario (full dwords at the st art and the end of each buffer), the absolute largest frame size is 2040 bytes (plus the automatically added fcs if enable). 11.11.3.2 calculating worst-case tx mil fifo usage the actual space consumed by a buffer in the tx mil fifo co nsists only of any partial dw ord offsets in the first/last dword of the buffer, plus all of t he whole dwords in between. any whole dword offsets and/or alignments are stripped off before the buffer is loaded into the tx data fifo, and tx command words are stripped off before the buffer is written to the tx mil fifo, so no ne of those dwords count as space cons umed. the worst-case overhead for a tx buffer is 6 bytes, which assumes that it started on the hi gh byte of a dword and ended on the low byte of a dword. a tx packet consisting of 86 such fragments woul d have an overhead of 516 bytes (6 * 86) which, when added to a 1514-byte max-size transmit packet (1516 bytes, rounded up to the next whole dword), would give a total space consumption of 2,032 bytes, leaving 4 bytes to spare; this is the basis for the 86 fragment rule mentioned above. for more information on th e mil fifos refer to section 11.10.2, "mil fifos," on page 157 . 11.11.4 tx status format tx status is passed to the host cpu through a separate fifo mechanism. a status word is returned for each packet transmitted. data transmission is suspended if the tx st atus fifo becomes full. data transmission will resume when the host reads the tx status and there is room in the fifo for more tx status data. the host can optionally choose to not read the tx status. the tx status can be ignored by setting the tx status discard allow overrun enable (txsao) bit in the transmit configuration register (tx_cfg) . setting this bit high allows the transmitter to continue operation with a full tx status fifo. in this mode the status information is still available in the tx status fifo, and tx status interrupts still function. in th e case of a full fifo, the txsused counter will stay at its maximum value and no further tx status will be written to th e tx status fifo, preventing an overrun, until the host frees space by reading tx status. in this mode the host is responsible for re-synchronizing tx status in the case of an overrun. bits description 31:16 packet tag. unique identifier written by the host into the packet tag field of the tx command b word. this field can be used by the host to correlate tx status words with the associated tx packets. 15 error status (es). when set, this bit indicates that the ethernet controller has reported an error. this bit is the logical or of bits 11, 10, 9, 8, 2, 1 in this status word. 14:12 reserved. these bits are reserved. always write zeros to this field to guarantee future compatibility. 11 loss of carrier. when set, this bit indicates the loss of carrier during transmission. 10 no carrier. when set, this bit indicates that the carrier signal from the transceiver was not present during transmission. 9 late collision. when set, indicates that the packet transmission was aborted after the collision window of 64 bytes. 8 excessive collisions. when set, this bit indicates that the transmission was aborted after 16 collisions while attempting to trans mit the current packet. 7 reserved. this bit is reserved. always write zeros to this field to guarantee future compatibility. 6:3 collision count. this counter indicates the number of collisions that occurred before the packet was transmitted. it is not valid when exce ssive collisions (bit 8) is also set. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 165 lan9250 11.11.5 calculating actual tx data fifo usage the following rules are used to calculate the act ual tx data fifo space consumed by a tx packet: tx command 'a' is stored in the tx data fifo for every tx buffer tx command 'b' is written into the tx data fifo when the first segment (fs) bit is set in tx command 'a' any dword-long data added as part of the data start of fset is removed from each buffer before the data is written to the tx data fifo. any data that is less than 1 dword is passed to the tx data fifo. payload from each buffer within a packet is written into the tx data fifo. any dword-long data added as part of the end padding is removed from each buffer before the data is written to the tx data fifo. any end padding that is less than 1 dword is passed to the tx data fifo 11.11.6 transmit examples 11.11.6.1 tx example 1 in this example a single, 111-byte ethernet packet will be trans mitted. this packet is divided into three buffers. the three buffers are as follows: buffer 0: 7-byte data start offset 79-bytes of payload data 16-byte buffer end alignment buffer 1: 0-byte data start offset 15-bytes of payload data 16-byte buffer end alignment buffer 2: 10-byte data start offset 17-bytes of payload data 16-byte buffer end alignment 2 excessive deferral. if the deferred bit is set in the control r egister, the setting of the excessive deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times during trans- mission. 1 reserved. this bit is reserved. 0 deferred. when set, this bit indicates that the current packet transmission was deferred. bits description downloaded from: http:///
lan9250 ds00001913a-page 166 ? 2015 microchip technology inc. figure 11-12 illustrates the tx command structure for this example, and also shows how data is passed to the tx data fifo. figure 11-12: tx example 1 tx command 'a' 0 31 tx command 'b' pad dword 1 7-byte data start offset 10-byte end padding 79-byte payload buffer end alignment = 1 data start offset = 7 first segment = 1 last segment = 0 buffer size = 79 packet length = 111 tx command 'a' 0 31 tx command 'b' 10-byte end offset padding 15-byte payload buffer end alignment = 1 data start offset = 0 first segment = 0 last segment = 0 buffer size = 15 packet length = 111 tx command 'a' 0 31 tx command 'b' buffer end alignment = 1 data start offset = 10 first segment = 0 last segment = 1 buffer size = 17 packet length = 111 10-byte data start offset tx command 'a' tx command 'b' tx command 'a' tx command 'b' tx command 'a' tx command 'b' note: extra bytes between buffers are not transmitted data written to the memory mapped tx data fifo port data passed to the tx data fifo 5-byte end padding 17-byte payload data tx command 'a' tx command 'b' tx command 'a' tx command 'a' 1b 79-byte payload 15-byte payload 17-byte payload downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 167 lan9250 11.11.6.2 tx example 2 in this example, a single 183-byte ethernet packet will be tr ansmitted. this packet is in a single buffer as follows: 2-byte data start offset 183-bytes of payload data 4-byte buffer end alignment figure 11-13 illustrates the tx command structure for this example, and also shows how data is passed to the tx data fifo. note that the packet resides in a single tx buffer, t herefore both the fs and ls bits are set in tx command a. figure 11-13: tx example 2 tx command 'a' 0 31 tx command 'b' data written to the memory mapped tx data fifo port tx command 'b' 183-byte payload data data start offset = 6 first segment = 1 last segment = 1 buffer size =183 packet length = 183 tx command 'a' tx command 'b' data passed to the tx data fifo buffer end alignment = 0 3b end padding tx command 'a' 6-byte data start offset 183-byte payload data note: extra bytes between buffers are not transmitted downloaded from: http:///
lan9250 ds00001913a-page 168 ? 2015 microchip technology inc. 11.11.6.3 tx example 3 in this example a single, 111-byte ethernet packet will be transmitted with a tx checksum. this packet is divided into four buffers. the four buffers are as follows: buffer 0: 4-byte data start offset 4-byte checksum preamble 16-byte buffer end alignment buffer 1: 7-byte data start offset 79-bytes of payload data 16-byte buffer end alignment buffer 2: 0-byte data start offset 15-bytes of payload data 16-byte buffer end alignment buffer 3: 10-byte data start offset 17-bytes of payload data 16-byte buffer end alignment figure 11-12, "tx example 1" illustrates the tx command struct ure for this example, and also shows how data is passed to the tx data fifo. note: in order to perform a tx checksum calculation on the associated packet, bit 14 (ck) of the tx command b must be set in conjunction with bit 13 (fs) of tx command a and the tx checksum offload engine enable (tx_coe_en) bit of the host mac checksum offload engine control register (hmac_coe_cr) . for more information, refer to section 11.8, "transmit che cksum offload engine (txcoe)" . downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 169 lan9250 figure 11-14: tx example 3 0 31 pad dword 1 7-byte data start offset 10-byte end padding buffer end alignment = 1 data start offset = 7 first segment = 0 last segment = 0 buffer size = 79 0 31 10-byte end offset padding buffer end alignment = 1 data start offset = 0 first segment = 0 last segment = 0 buffer size = 15 0 31 buffer end alignment = 1 data start offset = 10 first segment = 0 last segment = 1 buffer size = 17 10-byte data start offset tx command 'a' tx command 'b' tx command 'a' tx command 'b' tx command 'a' tx command 'b' note: extra bytes between buffers are not transmitted data written to the memory mapped tx data fifo port data passed to the tx data fifo 5-byte end padding 79-byte payload 15-byte payload 17-byte payload note: when enabled, the tx checksum preamble is pre-pended to data to be transmitted. the fs bit in tx command 'a', the ck bit in tx command 'b' and the txcoe_en bit in the coe_cr register must all be set for the tx checksum to be generated. fs must not be set for subsequent fragments of the same packet. 0 31 4-byte data start offset 8-byte end padding buffer end alignment = 1 data start offset = 4 first segment = 1 last segment = 0 buffer size = 4 packet length = 115 tx command 'a' tx command 'b' tx checksum location = 50 checksum preamble tx checksum start pointer = 14 tx checksum preamble tx checksum preamble 79-byte payload 15-byte payload 1b 17-byte payload data tx checksum enable = 1 packet length = 115 tx checksum enable = 1 packet length = 115 tx checksum enable = 1 packet length = 115 tx checksum enable = 1 tx command 'a' tx command 'b' tx command 'a' tx command 'b' tx command 'a' tx command 'b' tx command 'a' tx command 'b' tx command 'a' tx command 'b' tx command 'a' tx command 'a' tx command 'a' downloaded from: http:///
lan9250 ds00001913a-page 170 ? 2015 microchip technology inc. 11.11.7 transmitter errors if the transmitter error (txe) flag is a sserted for any reason, the transmitter will continue operation. tx error (txe) will be asserted under the following conditions: if the actual packet length count does not match t he packet length field as defined in the tx command. both tx command a and tx command b are required fo r each buffer in a given packet. tx command b must be identical for every buffer in a given packet. if the tx command b words do not match, the ethernet controller will assert the transmitter error (txe) flag. host overrun of the tx data fifo. 11.11.8 stopping and starting the transmitter to halt the transmitter, the host must set the stop_tx bit in the transmit configuration register (tx_cfg) . the trans- mitter will finish sending the current fr ame (if there is a frame transmission in progress). when the transmitter has received the tx status for this frame, it will clear the stop_tx and tx_on bi ts, and will pulse the txstop_int in the interrupt status register (int_sts) . once stopped, the host can optionally clear the tx status a nd tx data fifos. the host must re-enable the transmitter by setting the tx_on bit. if the there are frames pending in th e tx data fifo (i.e., tx data fifo was not purged), the transmission will resume with this data. 11.12 rx data path operation when an ethernet packet is received, the host mac interface layer (mil) first begi ns to transfer the rx data. this data is loaded into the rx data fifo. t he rx data fifo pointers are updated as data is written into the fifo. the last transfer from the mil is the rx status word. the device implements a separate fifo for the rx status words. the total available rx data and status queued in the rx fifo can be read from the rx fifo information register (rx_fifo_inf) . the host may read any number of available rx st atus words before reading the rx data fifo. the host must use caution when reading the rx data and st atus. the host must never read more data than what is available in the fifos. if this is attempted an underrun condi tion will occur. if this error occurs, the ethernet controller will assert the receiver error (rxe) inte rrupt. if an underrun condition occurs, a soft reset is required to regain host synchronization. a configurable beginning offset is supported in the device. the rx data offset field in the receive configuration reg- ister (rx_cfg) controls the number of bytes that the beginning of the rx data buffer is shifted. the host can set an offset from 0-31 bytes. the offset may be changed in between rx packets, but it must not be changed during an rx packet read. the device can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. this feature is necessary when the device is operating in a system that always performs multi-dword bursts. in su ch cases the device must guarantee that it can transfer data in multiples of the burst length regardless of the actual packet length. when configured to do so, the device will add extra data at the end of the packet to allow the host to perform the necessary number of reads so that the bu rst length is not cut short. once a packet has been padded by the h/w, it is the responsi bility of the host to interr ogate the packet length field in the rx status and determine how much padding to discard at the end of the packet. it is possible to read multiple packets out of the rx data fifo in one continuous stream. it should be noted that the programmed offset and padding will be added to each in dividual packet in the stream, since packet boundaries are maintained. 11.12.1 rx slave pio operation using pio mode, the host can either implement a polling or interrupt scheme to empty the received packet out of the rx data fifo. the host will remain in the idle state until it re ceives an indication (interrupt or polling) that data is avail- able in the rx data fifo. the host will then read the rx st atus fifo to get the packet status, which will contain the packet length and any other status information. the host should perform the proper number of reads, as indicated by the packet length plus the start offset and the amount of optional padding added to the end of the fr ame, from the rx data fifo. a typical host receive routine using interrupts can be seen in figure 11-15 , while a typical host receive rou- tine using polling can be seen in figure 11-16 . downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 171 lan9250 figure 11-15: host receive routine using interrupts figure 11-16: host receive routine using polling not last packet idle read rx status dword init read rx packet last packet rx interrupt not last packet read rx_fifo_inf read rx status dword init read rx packet last packet valid status dword downloaded from: http:///
lan9250 ds00001913a-page 172 ? 2015 microchip technology inc. 11.12.1.1 receive data fifo fast forward the rx data path implements an automatic data discar d function. using the rx da ta fifo fast forward bit (rx_ffwd) in the receive datapath control register (rx_dp_ctrl) , the host can instruct the device to skip the packet at the head of the rx data fifo. the rx data fifo pointers are automatically incremented to the beginning of the next rx packet. when performing a fast-forward, there must be at least 4 dwords of data in the rx data fifo for the packet being discarded. for cases with less than 4 dwords, do not use rx_ffwd. in this case data must be read from the rx data fifo and discarded using st andard pio read operations. after initiating a fast-forward operation, do not perform any r eads of the rx data fifo unt il the rx_ffwd bit is cleared. other resources can be accessed during this time (i.e., any regi sters and/or the other three fifos). also note that the rx_ffwd will only fast-forward the rx data fifo, not the rx status fifo. after an rx fast-forward operation the rx status must still be read from the rx status fifo. the receiver does not have to be st opped to perform a fast-forward operation. 11.12.1.2 force receiver discard (receiver dump) in addition to the receive data fast forward feature, device also implements a receiver dump feature. this feature allows the host processor to flush the entire contents of the rx data and rx status fi fos. when activated, the read and write pointers for the rx data and stat us fifos will be returned to their reset state. to perform a receiver dump, the device receiver must be halted. once the receiver stop completion is confirmed, the rx_dump bit can be set in the receive configuration register (rx_cfg) . the rx_dump bit is cleared when t he dump is complete. for more infor- mation on stopping the receiver, please refer to section 11.12.4, "stopping and starting the receiver" . for more infor- mation on the rx_dump bit, please refer to section 11.14.2, "receive confi guration register (rx_cfg)," on page 178 . 11.12.2 rx packet format the rx status words can be read from the rx status fifo port, while the rx data packets can be read from the rx data fifo. rx data packets are formatted in a specific manner before the host can read them as shown in figure 11- 17 . it is assumed that the host has previously read the associat ed status word from the rx status fifo, to ascertain the data size and any error conditions. figure 11-17: rx packet format ofs + first data dword .. . . last data dword 0 31 host read order 1st 2nd last optional pad dword0 .. optional pad dwordn optional offset dword0 .. optional offset dwordn downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 173 lan9250 11.12.3 rx status format bits description 31 packet filter. when set, this bit indicates that the associated frame passed the frame filtering described in section 11.5 . 30 filtering fail. when set, this bit indicates that the asso ciated frame failed the address recognizing fil- tering described in section 11.4 . 29:16 packet length. the size, in bytes, of the corresponding received frame. 15 error status (es). when set this bit indicates that the host mac interface layer (mil) has reported an error. this bit is the internal logical or of bits 11,7,6 and 1. 14 reserved. these bits are reserved. reads 0. 13 broadcast frame. when set, this bit indicates that th e received frame has a broadcast address. 12 length error (le). when set, this bit indicates that the actual length does not match with the length/ type field of the received frame. 11 runt frame. when set, this bit indicates that frame was prematurely terminated before the collision window (64 bytes). runt frames are passed on to th e host only if the pass bad frames bit (passbad) of the host mac control register (hmac_cr) is set. 10 multicast frame. when set, this bit indicates that the received frame has a multicast address. 9:8 reserved. these bits are reserved. reads 0. 7 frame too long. when set, this bit indicates that the frame length exceeds the maximum ethernet specification of 1518 bytes. this is only a frame to o long indication and will not cause the frame recep- tion to be truncated. 6 collision seen. when set, this bit indicates that the frame has seen a collision after the collision win- dow. this indicates that a late collision has occurred. 5 frame type. when set, this bit indicates that the frame is an ethernet-type frame (length/type field in the frame is greater than 1500). w hen reset, it indicates the inco ming frame was an 802.3 type frame. this bit is not set for runt frames less than 14 bytes. 4 receive watchd og time-out. when set, this bit indi cates that the incoming frame was greater than or equal to 2048 bytes, therefore expiring the receive watchdog timer. frames greater than or equal to 2049 bytes are truncated to 2048 bytes and woul d most likely have a crc error as a result. 3 mii error. when set, this bit indicates that a rece ive error was detected during frame reception. 2 dribbling bit. when set, this bit indicates that the frame contained a non-integer multiple of 8 bits. this error is reported only if the number of dribbling bits in the last byte is at least 3 in the 10 mbps operating mode. this bit will not be set when the collision seen bit[6] is set. if set and the crc error bit is [1] reset, then the packet is considered to be valid. 1 crc error. when set, this bit indicates that a crc error wa s detected. this bit is also set when the rx_er pin is asserted during the rec eption of a frame even though the crc may be correct. this bit is not valid if the received frame is a runt frame, or a late collision was detected. 0 reserved. these bits are reserved. reads 0 downloaded from: http:///
lan9250 ds00001913a-page 174 ? 2015 microchip technology inc. 11.12.4 stopping and starting the receiver to stop the receiver, the host must clear the rxen bit in the host mac control register (hmac_cr) . when the receiver is halted, the rxstop _int will be pulsed and reflected in the interrupt status register (int_sts) . once stopped, the host can optionally clear the rx status and rx data fifos. the host must re-enable the receiver by setting the rxen bit. 11.12.5 receiver errors if the receiver error (rxe) flag is asserted in the interrupt status register (int_sts) for any reason, the receiver will continue operation. rx error (rxe) will be asserted under the following conditions: a host underrun of rx data fifo a host underrun of the rx status fifo an overrun of the rx status fifo ( rx status fifo full interrupt (rsff) ) it is the duty of the host to identify and resolve any error conditions. 11.13 ieee 802.3az energy efficient ethernet the device supports energy efficient ethernet (eee) in 100 mbps mode as defined in the most recent version of the ieee 802.3az standard. energy efficient ethernet is enabled via host mac energy efficient ethernet (hmac_eee_enable) bit in the host mac control register (hmac_cr) . 11.13.1 tx lpi generation the process of when the mac should indicate lpi re quests to the phy is divided into two sections: client lpi requests to mac mac lpi request to phy 11.13.1.1 client lpi requests to mac when the tx fifo is empty for a time (in us) specified in host mac eee tx lpi request delay register (hmac_eee_tx_lpi_req_delay) a tx lpi request is asserted to the mac. a setting of 0 us is possible for this time. if the tx fifo becomes not empty while the timer is running, the timer is reset (i.e. empty time is not cumulative). once tx lpi is requested and the tx fifo become s not empty, the tx lpi request is negated. the tx fifo empty timer is reset if host mac energy efficient ethernet (hmac_eee_enable) in the host mac con- trol register (hmac_cr) is cleared. tx lpi requests are asserted only if the host mac energy efficient ethernet (hmac_eee_enable) bit is set, and if the current speed is 100 mbps, the current duplex is full (as indicated by the full duplex mode (fdpx) bit of the host mac control register (hmac_cr) ) and the auto-negotiation result indicates that both the local and partner device sup- port eee 100 mbps. in order to prevent an unstable link condition, the phy link stat us also must indicate up for one second before lpi is requested. tx lpi requests are asserted even if the transmitter enable (tx_on) bit in the transmit configuration register (tx_cfg) is cleared. 11.13.1.2 mac lpi request to phy lower power idle (lpi) is requested by the host ma c to the phy using the mii value of txen=0, txer=1, txd[3:0]=4b0001. the mac always finishes the current packet before signaling tx lpi to the phy. the mac will gen- erate tx lpi requests to the phy even if the transmitter enable (tx_on) bit in the transmit configuration register (tx_cfg) is cleared. 802.3az specifies the usage of a simplified full duplex mac with carrier sense deferral. basically this means that once the tx lpi request to the phy is de-asserted, the host mac will defer the time specified in host mac eee time wait tx system register (hmac_eee_tw_tx_sys) in addition to the normal ipg before sending a frame. tx lpi counters the host mac maintains a counter, eee tx lpi transitions , that counts the number of ti mes that tx lpi request to the phy changes from de-asserted to asserted. the counter is not writable and does not clear on read. the counter is reset if the host mac energy efficient ethernet (hmac_eee_enable) bit in the host mac control register (hmac_cr) is low. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 175 lan9250 the host mac maintains a counter, eee tx lpi time , that counts (in us) the amount of time that tx lpi request to the phy is asserted. note that this counter do es not include the time specified in the host mac eee time wait tx system register (hma c_eee_tw_tx_sys) . the counter is not writable and does not clear on read. the counter is reset if the host mac energy efficient ethernet (hmac_eee_enable) bit in the host mac control register (hmac_cr) is low. 11.13.2 rx lpi detection receive lower power idle (lpi) is indicated by the ph y to the mac using the mii value of rxdv=0, rxer=1, txd[3:0]=4b0001. 11.13.2.1 decoding lpi the mac will decode the lpi indication only when host mac energy efficient ethernet (hmac_eee_enable) is set in the host mac control register (hmac_cr) , and if the current speed is 100mbs, the current duplex is full (as indi- cated by the full duplex mode (fdpx) bit of the host mac control register (hmac_cr) ) and the auto-negotiation result indicates that both the local and partner device support s eee at 100mbs. in order to prevent an unstable link con- dition, the phy link status also must indicate up for one second is set.) before lpi is decoded. 11.13.2.2 rx lpi counters the host mac maintains a counter, eee rx lpi transitions , that counts the number of times that the lpi indication from the phy changes from de-asserted to asserted. the coun ter is not writable and does not clear on read. the counter is reset if the host mac energy efficient ethernet (hmac_eee_enable) bit in the host mac control register (hmac_cr) is low. the host mac maintains a counter, eee rx lpi time , that counts (in us) the amount of time that the phy indicates lpi. the counter is not writable and does not clear on read. the counter is reset if the host mac energy efficient ether- net (hmac_eee_enable) bit in the host mac control re gister (hmac_cr) is low. downloaded from: http:///
lan9250 ds00001913a-page 176 ? 2015 microchip technology inc. 11.14 host mac & fifo interface registers this section details the directly addressable host mac and tx/rx fifo related system csrs. these registers allow for the configuration of the tx/rx fifo s, host mac and indirect access to th e complete set of host mac csrs. the host mac csrs are accessible through via the host mac csr interface command register (mac_csr_cmd) and host mac csr interface data register (mac_csr_data) . note: for more information on the tx/rx fifos, refer to section 11.10, "fifos" . note: the full list of indirectly address able host mac csrs are described in section 11.15, "host mac control and status registers," on page 192 . table 11-15: host mac & fifo interface logic registers address register name (symbol) 068h fifo level interrupt register (fifo_int) 06ch receive configuration register (rx_cfg) 070h transmit configuration register (tx_cfg) 078h receive datapath control register (rx_dp_ctrl) 07ch rx fifo information register (rx_fifo_inf) 080h tx fifo information register (tx_fifo_inf) 0a0h host mac rx dropped frames counter register (rx_drop) 0a4h host mac csr interface command register (mac_csr_cmd) 0a8h host mac csr interface data register (mac_csr_data) 0ach host mac automatic flow contro l configuration register (afc_cfg) 0b0h host mac rx lpi transitions register (hmac_rx_lpi_transition) 0b4h host mac rx lpi time register (hmac_rx_lpi_time) 0b8h host mac tx lpi transitions register (hmac_tx_lpi_transition) 0bch host mac tx lpi time register (hmac_tx_lpi_time) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 177 lan9250 11.14.1 fifo level interr upt register (fifo_int) this read/write regist er configures the limits where the rx/tx data and status fifos will g enerate system interrupts. offset: 068h size: 32 bits bits description type default 31:24 tx data available level the value in this field sets the level, in number of 64 byte blocks, at which the tx data fifo available interrupt (tdfa) will be generated. when the tx data fifo free space is greater than this value, a tx data fifo available interrupt (tdfa) will be generated in the interrupt status register (int_sts) . r/w 48h 23:16 tx status level the value in this field sets the leve l, in number of dwords, at which the tx status fifo level interrupt (tsfl) will be generated. when the tx status fifo used space is greater than this value, a tx status fifo level interrupt (tsfl) will be generated in the interrupt status register (int_sts) . r/w 00h 15:8 reserved ro - 7:0 rx status level the value in this field sets the level, in number of dwords, at which the rx status fifo level interrupt (rsfl) will be generated. when the rx status fifo used space is greater than this value, a rx status fifo level interrupt (rsfl) will be generated in the interrupt status register (int_sts) . r/w 00h downloaded from: http:///
lan9250 ds00001913a-page 178 ? 2015 microchip technology inc. 11.14.2 receive configurat ion register (rx_cfg) this register controls the host mac receive engine. offset: 06ch size: 32 bits bits description type default 31:30 rx end alignment (rx_ea) this field specifies the alignment that must be maintained on the last data transfer of a buffer. the device will a dd extra dwords of data up to the alignment specified in the table below. the host is responsible for removing these extra dwords. this mechanism can be used to maintain cache line alignment on host processors. note: the desired rx end alignment must be set before reading a packet. the rx end alignment can be changed between reading receive packets, but must not be changed if the packet is partially read. r/w 00b 29:28 reserved ro - 27:16 rx dma count (rx_dma_cnt) this 12-bit field indicates the amount of data, in dwords, to be transferred out of the rx data fi fo before asserting the rx dma interrupt (rxd_int) . after being set, this field is decremented for each dword of data that is read from the rx data fifo. this field can be overwritten with a new value before it reaches zero. r/w 000h 15 force rx discard (rx_dump) when a 1 is written to this bit, the rx data and status fifos are cleared of all pending data and the rx data and status pointers are cleared to zero. note: please refer to section 11.12.1.2, "for ce receiver discard (receiver dump)," on page 172 for a detailed description regarding the use of rx_dump. wo sc 0b 14:13 reserved ro - bit values [31:30] end alignment 00 4-byte alignment 01 16-byte alignment 10 32-byte alignment 11 reserved downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 179 lan9250 12:8 rx data offset (rxdoff) this field controls the offset value, in bytes, that is added to the beginning of an rx data packet. the start of the valid data will be shifted by the number of bytes specified in this field. an offs et of 0-31 bytes is a valid number of offset bytes. note: the two lsbs of this field (d[9:8]) must not be modified while the rx is running. the receiver must be halted, and all data purged before these two bits can be modified. the upper three bits (dword offset) may be modified while the receiver is running. modifications to the upper bits w ill take affect on the next dword read. r/w 00000b 7:0 reserved ro - bits description type default downloaded from: http:///
lan9250 ds00001913a-page 180 ? 2015 microchip technology inc. 11.14.3 transmit configuration register (tx_cfg) this register controls the host mac transmit functions. offset: 070h size: 32 bits bits description type default 31:16 reserved ro - 15 force tx status discard (txs_dump) when a 1 is written to this bit, the tx status fifo is cleared of all pending status dwords and the tx status pointers are cleared to zero. wo sc 0b 14 force tx data discard (txd_dump) when a 1 is written to this bit, the tx da ta fifo is cleared of all pending data and the tx data pointers are cleared to zero. wo sc 0b 13:3 reserved ro - 2 tx status allow overrun (txsao) when this bit is cleared, host mac data transmission is suspended if the tx status fifo becomes full. setting this bit high allows the transmitter to con- tinue operation with a full tx status fifo. note: this bit does not affect the operation of the tx status fifo full interrupt (tsff) . r/w 0b 1 transmitter en able (tx_on) when this bit is set, the host mac trans mitter is enabled. any data in the tx data fifo will be sent. this bit is cleared automatically when the stop_tx bit is set and the transmitter is halted. r/w 0b 0 stop transmitter (stop_tx) when this bit is set, the host mac trans mitter will finish the current frame, and will then stop transmitting. when the transmitter has stopped this bit will clear. all writes to this bit are ignored while this bit is high. r/w sc 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 181 lan9250 11.14.4 receive datapath control register (rx_dp_ctrl) this register is used to discard unwanted receive frames. offset: 078h size: 32 bits bits description type default 31 rx data fifo fast forward (rx_ffwd) writing a 1 to this bit causes the rx data fifo to fast-forward to the start of the next frame. this bit will remain high until the rx data fifo fast-forward operation has completed. no reads shou ld be issued to the rx data fifo while this bit is high. note: please refer to section section 11.12.1.1, "rec eive data fifo fast forward," on page 172 for detailed information regarding the use of rx_ffwd. r/w sc 0h 30:0 reserved ro - downloaded from: http:///
lan9250 ds00001913a-page 182 ? 2015 microchip technology inc. 11.14.5 rx fifo informatio n register (rx_fifo_inf) this register contains the indication of used space in the rx fifos. offset: 07ch size: 32 bits bits description type default 31:24 reserved ro - 23:16 rx status fifo used space (rxsused) this field indicates the amount of spac e, in dwords, currently used in the rx status fifo. ro 0b 15:0 rx data fifo used space (rxdused) this field indicates the amount of space, in bytes, used in the rx data fifo. for each receive frame, the field is in cremented by the length of the receive data. in cases where the payload does not end on a dword boundary, the total will be rounded up to the nearest dword. ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 183 lan9250 11.14.6 tx fifo informatio n register (tx_fifo_inf) this register contains the indication of free space in th e tx data fifo and the used space in the tx status fifo. offset: 080h size: 32 bits bits description type default 31:24 reserved ro - 23:16 tx status fifo used space (txsused) this field indicates the amount of spac e, in dwords, currently used in the tx status fifo. ro 0b 15:0 tx data fifo free space (txfree) this field indicates the amount of space, in bytes, available in the tx data fifo. the application should never write mo re than is available, as indicated by this value. ro 1200h downloaded from: http:///
lan9250 ds00001913a-page 184 ? 2015 microchip technology inc. 11.14.7 host mac rx dropped fr ames counter register (rx_drop) this register indicates the number of receive frames that have been dropped by the host mac. offset: 0a0h size: 32 bits bits description type default 31:0 rx dropped frame counter (rx_dfc) this counter is incremented every ti me a receive frame is dropped by the host mac. rx_dfc is cleared on any read of this register. note: the interrupt rxdfh_int (bit 23 of the interrupt status register (int_sts) ) can be issued when this counter passes through its halfway point (7fffffffh to 80000000h). rc 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 185 lan9250 11.14.8 host mac csr interface co mmand register (mac_csr_cmd) this read-write register is used to control the read and writ e operations to/from the host mac. this register in used in conjunction with the host mac csr interface data register (mac_csr_data) to indirectly access the host mac csrs. note: the full list of host mac csrs are described in section 11.15, "host mac control and status registers," on page 192 . offset: 0a4h size: 32 bits bits description type default 31 host mac csr busy (hmac_csr_busy) when a 1 is written into this bit, the read or write operation is performed to the specified host mac csr. this bit will remain set until the operation is complete. in the case of a read, this indicates that the host can read valid data from the host mac csr interface data register (mac_csr_data) . note: the mac_csr_cmd and mac_csr_data registers must not be modified until this bit is cleared. r/w sc 0b 30 r/nw when set, this bit indicates that the host is requesting a read operation. when clear, the host is performing a write. 0: host mac csr write operation 1: host mac csr read operation r/w 0b 29:8 reserved ro - 7:0 csr address the 8-bit value in this field selects which host mac csr will be accessed by the read or write operation. the inde x of each host mac csr is defined in section 11.15, "host mac control and status registers," on page 192 . r/w 00h downloaded from: http:///
lan9250 ds00001913a-page 186 ? 2015 microchip technology inc. 11.14.9 host mac csr interface data register (mac_csr_data) this read-write register is used in conjunction with the host mac csr interface command register (mac_csr_cmd) to indirectly access the host mac csrs. note: the full list of host mac csrs are described in section 11.15, "host mac control and status registers," on page 192 . offset: 0a8h size: 32 bits bits description type default 31:0 host mac csr data this field contains the value read from or written to the host mac csr as specified in the host mac csr interface command register (mac_cs- r_cmd) . upon a read, the value returned depends on the r/nw bit in the mac_csr_cmd register. if r/nw is a 1, t he data in this register is from the host mac. if r/nw is 0, the data is th e value that was last written into this register. note: the mac_csr_cmd and mac_csr_data registers must not be modified until the csr busy bit is cleared in the mac_csr_cmd register. r/w 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 187 lan9250 11.14.10 host mac automatic flow cont rol configuration register (afc_cfg) this read/write register co nfigures the mechanism that controls the au tomatic and software-initiated transmission of pause frames and back pressure from the host mac to t he network. this register is used in conjunction with the host mac flow control register (hmac_flow) in the host mac csr space. pause frames and backpressure are sent to the network to stop it from s ending packets to the host mac. note: the host mac will not transmit pause frames or asse rt back pressure if the transmitter is disabled. refer to section section 11.2, "flow control," on page 139 for additional information. offset: 0ach size: 32 bits bits description type default 31:24 reserved ro - 23:16 automatic flow control high level (afc_hi) this field specifies, in multiples of 64 by tes, the level at which flow control will trigger. when this limit is reached, the chip will apply back pressure or will transmit a pause frame as programmed in bits [3:0] of this register. during full-duplex operation only a si ngle pause frame is transmitted when this level is reached. the pause time transmitted in this frame is programmed in the fcpt field of the host mac flow control register (hmac_flow) in the host mac csr space. during half-duplex operation each incoming frame that matches the criteria in bits [3:0] of this register will be jammed for the period set in the back_dur field. r/w 00h 15:8 automatic flow control low level (afc_lo) this field specifies, in multiples of 64 bytes, the level at which a pause frame is transmitted with a pause time setting of zero. when the amount of data in the rx data fifo falls below this le vel the pause frame is transmitted. a pause time value of zero instructs the other transmit ting device to immedi- ately resume transmission. the zero time pause frame will only be transmit- ted if the rx data fifo had reached the afc_hi level and a pause frame was sent. a zero pause time frame is sent whenever automatic flow control in enabled in bits [3:0] of this register. note: when automatic flow control is enabled the afc_lo setting must always be less than the afc_hi setting. r/w 00h 7:4 backpressure duration (back_dur) when the host mac automatically assert s back pressure, it will be asserted for this period of time. in full-duplex mode, this field has no function and is not used. please refer to table 11-16 , describing backpressure duration bit map- ping for more information. r/w 0h 3 flow control on multicast frame (fcmult) when this bit is set, the host mac wi ll assert back pressu re when the afc level is reached and a multicast frame is received. this field has no function in full-duplex mode. 0: flow control on multicast frame disabled 1: flow control on multicast frame enabled r/w 0b downloaded from: http:///
lan9250 ds00001913a-page 188 ? 2015 microchip technology inc. 2 flow control on broadcast frame (fcbrd) when this bit is set, the host mac will assert back pressure when the afc level is reached and a broadcast frame is received. this field has no function in full-duplex mode. 0: flow control on broadcast frame disabled 1: flow control on broadcast frame enabled r/w 0b 1 flow control on address decode (fcadd) when this bit is set, the host mac will assert back pressure when the afc level is reached and a frame addressed to the host mac is received. this field has no function in full-duplex mode. 0: flow control on ad dress decode disabled 1: flow control on address decode enabled r/w 0b 0 flow control on any frame (fcany) when this bit is set, the host mac wi ll assert back pressure, or transmit a pause frame when the afc level is reached and any frame is received. set- ting this bit enables full-duplex flow control when the host mac is operating in full-duplex mode. when this mode is enabled during half- duplex operation, the flow controller does not decode the host mac address and will send a jam upon receipt of a valid preamble (i.e., immediately at t he beginning of the next frame after the rx data fifo level is reached). when this mode is enabled during full-duplex operation, the flow controller will immediately instruct the host mac to send a pause frame when the rx data fifo level is reached. the mac will queue the pause frame transmis- sion for the next available window. setting this bit overrides bits [3:1] of this register. r/w 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 189 lan9250 note: backpressure duration is timed from when the rx fifo reaches the level set in automatic flow control high level (afc_hi) , regardless when actual backpressure occurs. table 11-16: backpressure duration bit mapping backpressure duration [7:4] 100mbs mode 10mbs mode 0h 5 us 7.2 us 1h 10 us 12.2 us 2h 15 us 17.2 us 3h 25 us 27.2 us 4h 50 us 52.2 us 5h 100 us 102.2 us 6h 150 us 152.2 us 7h 200 us 202.2 us 8h 250 us 252.2 us 9h 300 us 302.2 us ah 350 us 352.2 us bh 400 us 402.2 us ch 450 us 452.2 us dh 500 us 502.2 us eh 550 us 552.2 us fh 600 us 602.2 us downloaded from: http:///
lan9250 ds00001913a-page 190 ? 2015 microchip technology inc. 11.14.11 host mac rx lpi transition s register (hmac_rx_lpi_transition) this register indicates the number of times that the rx lpi indication fr om the phy changed from de-asserted to asserted. 11.14.12 host mac rx lpi time register (hmac_rx_lpi_time) this register shows the total duration that the phy has indicated rx lpi. offset: 0b0h size: 32 bits bits description type default 31:0 eee rx lpi transitions count of total number of times that the rx lpi indication from the phy changed from de-asserted to asserted. the counter is reset if the host mac energy efficient ethernet (hmac_eee_enable) bit in the host mac control register (hmac_cr) is low. ro 00000000h offset: 0b4h size: 32 bits bits description type default 31:0 eee rx lpi time this field shows the total duration, in us, that the phy has indicated rx lpi. the counter is reset if the host mac energy efficient ethernet (hmac_eee_enable) bit in the host mac control register (hmac_cr) is low. ro 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 191 lan9250 11.14.13 host mac tx lpi transition s register (hmac_tx_lpi_transition) this register indicates the total numbe r of times tx lpi request to the phy changed from de-asserted to asserted. 11.14.14 host mac tx lpi time register (hmac_tx_lpi_time) this register shows the total duration that tx lpi request to the phy has been asserted. offset: 0b8h size: 32 bits bits description type default 31:0 eee tx lpi transitions count of total number of times the tx lpi request to the phy changed from de-asserted to asserted. the counter is reset if the host mac energy efficient ethernet (hmac_eee_enable) bit in the host mac control register (hmac_cr) is low. ro 00000000h offset: 0bch size: 32 bits bits description type default 31:0 eee tx lpi time this field shows the total duration, in us, that tx lpi request to the phy has been asserted. the counter is reset if the host mac energy efficient ethernet (hmac_eee_enable) bit in the host mac control register (hmac_cr) is low. ro 00000000h downloaded from: http:///
lan9250 ds00001913a-page 192 ? 2015 microchip technology inc. 11.15 host mac control and status registers this section details the indirectly addressable host mac system csrs. these registers are located in the host mac and are accessed indirectly via the system csrs. table 11-17 lists host mac registers that are accessible through the indexing method using the host mac csr interface command register (mac_csr_cmd) and host mac csr inter- face data register (mac_csr_data) . the host mac registers allow configuration of the various host mac parameters including the host mac address, flow control, multicast hash table, and wake -up configuration. the host mac csrs also provide serial access to the phy via the registers hmac_mii_acc and hmac_mii_data. these registers allow access to the 10/100 ethernet phy reg- isters. table 11-17: host mac addressable registers address (indirect) register name (symbol) 00h reserved for future use (reserved) 01h host mac control register (hmac_cr) 02h host mac address high register (hmac_addrh) 03h host mac address low register (hmac_addrl) 04h host mac multicast hash table high register (hmac_hashh) 05h host mac multicast hash table low register (hmac_hashl) 06h host mac mii access register (hmac_mii_acc) 07h host mac mii data register (hmac_mii_data) 08h host mac flow control register (hmac_flow) 09h host mac vlan1 tag register (hmac_vlan1) 0ah host mac vlan2 tag register (hmac_vlan2) 0bh host mac wake-up frame filter register (hmac_wuff) 0ch host mac wake-up control and status register (hmac_wucsr) 0dh host mac checksum offl oad engine cont rol register (hmac_coe_cr) 0eh host mac eee time wait tx system register (hmac_eee_tw_tx_sys) 0fh host mac eee tx lpi request delay r egister (hmac_eee_tx_lpi_req_delay) 10h-ffh reserved for future use (reserved) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 193 lan9250 11.15.1 host mac control register (hmac_cr) this read/write register establishes the rx and tx operation modes and controls fo r address filtering and packet filter- ing. offset: 01h size: 32 bits bits description type default 31 receive all mode (rxall) when set, all incoming packets will be received and passed on to the address filtering function for processing of the selected filtering mode on the received frame. address filtering then occurs and is reported in receive sta- tus. when cleared, only frames that pa ss destination address filtering will be sent to the application. r/w 0b 30:26 reserved ro - 25 host mac energy efficient ethernet (hmac_eee_enable) when set, this bit enables eee operation (both tx lpi and rx lpi) r/w note 7 24 reserved ro 0b 23 disable receive own (rcvown) when set, the host mac disables the rece ption of frames when it is transmit- ting (txen output is asserted). when cleared, the host mac receives all packets, including those transmitted by the host mac. this bit has no effect when the full duplex mode (fdpx) bit is set. r/w 0b 22 reserved ro - 21 loopback operation mode (loopbk) selects the loop back operation modes fo r the host mac. this field is only valid for full duplex mode. in internal loopback mode, the tx frame is received by the internal mii interface, and sent back to the host mac without being sent to the network. 0: normal operation. loopback disabled. 1: loopback enabled note: when enabling or disabling the loopback mode it can take up to 10 ? s for the mode change to occur. the transmitter and receiver must be stopped and di sabled when modifyi ng the loopbk bit. the transmitter or receiver should not be enabled within10 ? s of modifying the loopbk bit. r/w 0b 20 full duplex mode (fdpx) when set, the host mac operates in full -duplex mode, in which it can trans- mit and receive simultaneously. r/w 0b 19 pass all multicast (mcpas) when set, indicates that all incoming frames with a multicast destination address (first bit in the destination addr ess field is 1) are received. incoming frames with physical address (individ ual address/unicast) destinations are filtered and received only if the address matches the host mac address. r/w 0b 18 promiscuous mode (prms) when set, indicates that any incoming frame is received regardless of its destination address. r/w 1b downloaded from: http:///
lan9250 ds00001913a-page 194 ? 2015 microchip technology inc. 17 inverse filtering (invfilt) when set, the address check function oper ates in inverse filtering mode. this is valid only during perfect filtering mode. refer to section 11.4.4, "inverse filtering," on page 143 for additional information. r/w 0b 16 pass bad frames (passbad) when set, all incoming frames that passed address filtering are received, including runt frames and collided frames. refer to section 11.4, "address filtering," on page 142 for additional information. r/w 0b 15 hash only filtering mode (ho) when set, the address check function operates in the imperfect address fil- tering mode for both physical and multicast addresses. refer to section 11.4.2, "hash only filtering," on page 143 for additional information. r/w 0b 14 reserved ro - 13 hash/perfect filter ing mode (hpfilt) when cleared (0), the device will implement a perfect address filter on incom- ing frames according the address specified in the host mac address regis- ters ( host mac address high register (hmac_addrh) and host mac address low register (hmac_addrl) ). when set (1), the address check functi on performs imperfect address filtering of multicast incoming frames according to the hash table specified in the mul- ticast hash table register. if the hash on ly filtering mode (ho) bit 15 is set, then the physical (ia) addresses are also imperfect filtered. if the hash only filtering mode (ho) bit is cleared, then the ia addresses are perfect address filtered according to the mac address register refer to section 11.4.3, "hash perfect filtering," on page 143 for additional information. r/w 0b 12 reserved ro 0b 11 disable broadcast frames (bcast) when set, disables the reception of broadcast frames. when cleared, for- wards all broadcast frames to the application. note: when wake-up frame detection is e nabled via the wuen bit of the host mac wake-up control and status register (hmac_wucsr) , a broadcast wake-up frame will wa ke-up the device despite the state of this bit. r/w 0b 10 disable retry (disrty) when set, the host mac attempts only one transmission. when a collision is seen on the network, the host mac ignores the current frame and goes to the next frame and a retry error is re ported in the transmit status. when reset, the host mac attempts 16 transmissions before signaling a retry error. r/w 0b 9 reserved ro - 8 automatic pad stripping (padstr) when set, the host mac strips the pad field on all incoming frames, if the length field is less than 46 bytes. the fcs field is also stripped, since it is computed at the transmitting station ba sed on the data and pad field charac- ters, and is invalid for a received fr ame that has had the pad characters stripped. receive frames with a 46-byte or greater length field are passed to the application unmodified (fcs is not stripped). when cleared, the host mac passes all incoming frames to the host unmodified. r/w 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 195 lan9250 7:6 backoff limit (bolmt) the bolmt bits allow the user to set t he back-off limit in a relaxed or aggres- sive mode. according to ieee 802.3, the host mac has to wait for a random number [r] of slot-times (see note) after it detects a collision, where: (eq.1)0 < r < 2 k the exponent k is dependent on how many times the current frame to be transmitted has been retried, as follows: (eq.2)k = min (n, 10) where n is the current number of retries. if a frame has been retried three times, then k = 3 and r= 8 slot-times maxi- mum. if it has been retried 12 times, then k = 10, and r = 1024 slot-times maximum. an lfsr (linear feedback shift register) 20-bit counter emulates a 20 bit ran- dom number generator, from which r is obtained. once a collision is detected, the number of the current retry of the cu rrent frame is used to obtain k (eq.2). this value of k translates into the number of bits to use from the lfsr counter. if the value of k is 3, the ho st mac takes the value in the first three bits of the lfsr counter and uses it to count down to zero on every slot-time. this effectively causes the host mac to wait eight slot-times. to give the user more flexibility, the bolmt value forces the number of bits to be used from the lfsr counter to a predetermined value as in the table below. thus, if the value of k = 10, the host mac will look at the bo lmt if it is 00b, then use the lower ten bits of the lfsr counter for the wait countdown. if the bolmt is 10b, then it will only use the value in the first four bits for the wait countdown, etc. note: slot-time = 512 bit times. (see i eee 802.3 spec., se ctions 4.2.3.25 and 4.4.2.1) r/w 0b 5 deferral check (dfchk) when set, enables the deferral check in the host mac. the host mac will abort the transmission attempt if it has deferred for more than 24,288 bit times. deferral starts when the transmitter is ready to transmit, but is pre- vented from doing so because the crs is active. deferral time is not cumula- tive. if the transmitter defers for 10,000 bit times, then tr ansmits, collides, backs off, and then has to defer again after completion of back-off, the defer- ral timer resets to 0 and restarts. when this bit is cleared, the deferral check is disabled in the host mac and the host mac defers indefinitely. r/w 0b 4 reserved ro - 3 transmitter enable (txen) when set, the host macs transmitter is enabled and it will transmit frames from the buffer. when cleared, the host macs transmitter is disabled and will not transmit any frames. r/w 0b 2 receiver enable (rxen) when set, the host macs receiver is enabled and will receive frames. when cleared, the macs receiver is disabled and will not receive any frames. r/w 0b bits description type default bolmt value # bits used from lfsr counter 00b 10 01b 8 10b 4 11b 1 downloaded from: http:///
lan9250 ds00001913a-page 196 ? 2015 microchip technology inc. note 7: the value of this field is determined by the eee_enable_strap_1 (default 1b). 1:0 reserved ro - bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 197 lan9250 11.15.2 host mac address high register (hmac_addrh) this read/write register contai ns the upper 16-bits of the physical address of the host mac. the cont ents of this register are optionally loaded from the eeprom at power-o n through the eeprom loader if a programmed eeprom is detected. the least signif icant byte of this register (bits [7:0]) is loaded from address 05h of the eeprom. the second byte (bits [15:8]) is loaded from address 06h of the eeprom. section 11.9, "host mac address," on page 156 details the byte ordering of the hmac_addrl and hmac_addrh registers with respect to the reception of the ethernet phys- ical address. please refer to section 13.4, "eeprom loader," on page 290 for more information on the eeprom loader. this register used to specif y the address used for perfect da, magic packe t and wakeup frames, the unicast destination address for received pause frames, and the source address for transmitted pause frames. this register is not used for packet filtering. offset: 02h size: 32 bits bits description type default 31:16 reserved ro - 15:0 physical address [47:32] this field contains the upper 16-bits (47:32) of the physical address of the host mac. the content of this field is undefined until loaded from the eeprom at power-on. the host can update the contents of this field after the initialization process has completed. r/w ffffh downloaded from: http:///
lan9250 ds00001913a-page 198 ? 2015 microchip technology inc. 11.15.3 host mac address low register (hmac_addrl) this read/write register cont ains the lower 32-bits of the physical address of the host mac. the contents of this register are optionally loaded from the eeprom at power-on through the eeprom loader if a programmed eeprom is detected. the least sign ificant byte of this register (bits [7:0]) is loaded from address 01h of the eeprom. the most significant byte of this register is loaded from address 04h of the eeprom. section 11.9, "host mac address," on page 156 details the byte ordering of the hmac_addrl and hmac_addrh registers with respect to the reception of the ethernet physical address. please refer to section 13.4, "eeprom loader," on page 290 for more information on the eeprom loader. this register used to specify the address used for perfect da, magic packet and wakeup frames, the unicast destination address for received pause frames, and the source address for transmitted pause frames. this register is not used for packet filtering. offset: 03h size: 32 bits bits description type default 31:0 physical address [31:0] this field contains the lower 32-bits (31:0) of the physical address of the host mac. the content of this fiel d is undefined until loaded from the eeprom at power-on. the host can update the contents of this field after the initialization process has completed. r/w ffffffffh downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 199 lan9250 11.15.4 host mac multicast hash t able high register (hmac_hashh) the 64-bit multicast table is used for gr oup address filtering. for hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the ha sh table. the most significant bit determines the register to be used (hi/low), while the other five bits determine the bit within the register. a value of 00000 selects bit 0 of the multicast hash table lo register and a value of 11111 sele cts the bit 31 of the multicast hash table hi register. if the corresponding bit is 1, then the mult icast frame is accepted. otherwise, it is rejected. if the pass all multica st (mc pas) bit of the host mac control register (hmac_cr) is set, then all multicast frames are accepted regardless of the multicast hash values. the multicast hash table high register contains the higher 32 bits of the hash table and the multicast hash table low register contains the lower 32 bits of the hash table. refer to section 11.4, "address filtering," on page 142 for more information on address filtering. 11.15.5 host mac multicast hash table low register (hmac_hashl) this read/write register defines the lower 32-bits of the multicast hash table. please refer to the host mac multicast hash table high register (hmac_hashh) and section 11.4, "address filtering," on page 142 for more information. offset: 04h size: 32 bits bits description type default 31:0 upper 32-bits of the 64-bit hash table r/w 00000000h offset: 05h size: 32 bits bits description type default 31:0 lower 32-bits of the 64-bit hash table r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 200 ? 2015 microchip technology inc. 11.15.6 host mac mii access register (hmac_mii_acc) this read/write register is used in conjunction with the host mac mii data register (hmac_mii_data) to access the internal phy registers. refer to section 12.2.18, "phy registers" for a list of accessible phy registers and phy address information. offset: 06h size: 32 bits bits description type default 31:16 reserved ro - 15:11 phy address (phy_addr) this field must be loaded with the phy address that the mii access is intended for. refer to section 12.1.1, "phy addressing," on page 210 for additional information on phy addressing. r/w 00000b 10:6 mii register index (miirinda) these bits select the desir ed mii register in the phy. r/w 00000b 5:2 reserved ro - 1 mii write (miiwnr) setting this bit tells the phy that this will be a write operation using the host mac mii data register (hmac_mii_data) . if this bit is cleared, a read oper- ation will occur, packing the data in the host mac mii data register (hmac_mii_data) . r/w 0b 0 mii busy (miibzy) this bit must be polled to determine when the mii register access is com- plete. this bit must read a logical 0 before writing to this register or the host mac mii data register (hmac_mii_data) . the lan driver software must set this bit in order for the device to read or write any of the mii phy registers. during a mii register access, this bit w ill be set, signifying a read or write access is in progress. the mii data regi ster must be kept valid until the host mac clears this bit during a phy write operation. the mii data register is invalid until the host mac has cleared this bit during a phy read operation. ro sc 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 201 lan9250 11.15.7 host mac mii data register (hmac_mii_data) this read/write register is used in conjunction with the host mac mii access register (hmac_mii_acc) to access the internal phy registers. this register contains either th e data to be written to the ph y register specified in the hmac_mii_acc register, or the read data from the phy regi ster whose index is specifie d in the hmac_mii_acc reg- ister. the mii busy (miibzy) bit in the host mac mii access re gister (hmac_mii_acc) must be cleared when writing to this register. offset: 07h size: 32 bits bits description type default 31:16 reserved ro - 15:0 mii data this field contains the 16-bit value read from the phy read operation or the 16-bit data value to be written to the phy before an mii write operation. r/w 0000h downloaded from: http:///
lan9250 ds00001913a-page 202 ? 2015 microchip technology inc. 11.15.8 host mac flow control register (hmac_flow) this read/write register controls the generation and rece ption of the control (pause command) frames by the host macs flow control block. the control frame fields are sele cted as specified in the 802.3 specification and the pause- time value from this register is used in the pause time field of the control frame. in full-duplex mode the fcbsy bit is set until the control frame is comple tely transferred. the host has to make sure that the fcbsy bi t is cleared before writing the register. the pass control frame bit (fcpass) does not affect the sending of the frames, including control frames, to the host. the flow control enable (fcen) bi t enables the receive portion of the flow control block. this register is used in conjunction with the host mac automatic flow control configuration register (afc_cfg) in the system csrs to configure flow control. software flow control is initiated using the afc_cfg register. the host mac will not transmit pause frames or asse rt back pressure if the transmitter is disabled. offset: 08h size: 32 bits bits description type default 31:16 pause time (fcpt) this field indicates the value to be used in the pause time field in the con- trol frame. this field must be initialized before full-duplex automatic flow con- trol is enabled. r/w 0000h 15:3 reserved ro - 2 pass control frames (fcpass) when set, the host mac sets the packet fi lter bit in the receive packet status to indicate to the application that a valid pause frame has been received. the application must accept or discard a received frame based on the packet fil- ter control bit. the host mac receiv es, decodes and performs the pause function when a valid pause frame is received in full-duplex mode and when flow control is enabled (fce bit set). when this bit is cleared, the host mac resets the packet filter bit in the receive packet status. the host mac always passes the data of all frames it receives (including flow control frames) to the application. frames that do not pass address filter- ing, as well as frames with errors, ar e passed to the application. the applica- tion must discard or retain the received frames data based on the received frames status field. filtering modes (promiscuous mode, for example) take precedence over the fcpass bit. r/w 0b 1 flow control enable (fcen) when set, enables the host mac flow control function. the host mac decodes all incoming frames for control frames; if it receives a valid control frame (pause command), it disables the transmitter for a specified time (decoded pause time x slot time). when this bit is cleared, the host mac flow control function is disabled; the mac does not decode frames for control frames. note: flow control is applicable when the host mac is set in full duplex mode. in half-duplex mode, this bit enables the backpressure function to control the flow of received frames to the host mac. r/w 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 203 lan9250 0 flow control busy (fcbsy) in full-duplex mode, this bit indicates that the host mac is in the process of sending a pause control frame. this bit is set by the automatic flow control function. during the transmission of the control frame, this bit continues to be set, sig- nifying that a frame transmission is in progress. after the pause control frames transmission is complete, the host mac resets the bit to 0. the host software should read a logical 0 from this bit before writing to the host mac flow control (hmac_flow) register. r/w sc 0b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 204 ? 2015 microchip technology inc. 11.15.9 host mac vlan1 tag register (hmac_vlan1) this read/write register contains the vlan tag field to identify vlan1 frames. when a vlan1 frame is detected, the legal frame length is increased from 1518 bytes to 1522 bytes. refer to section 11.3, "virtual local area network (vlan) support," on page 140 for additional information. 11.15.10 host mac vlan2 ta g register (hmac_vlan2) this read/write register contains the vlan tag field to identify vlan2 frames. when a vlan2 frame is detected, the legal frame length is increased from 1518 bytes to 1538 bytes. refer to section 11.3, "virtual local area network (vlan) support," on page 140 for additional information. offset: 09h size: 32 bits bits description type default 31:16 reserved ro - 15:0 vlan1 tag identifier (vti1) this field contains the vlan tag used to identify vlan1 frames. this field is compared with the 13th and 14th bytes of the incoming frames for vlan1 frame detection. note: if used, this register is typically set to the standard vlan value of 8100h. r/w ffffh offset: 0ah size: 32 bits bits description type default 31:16 reserved ro - 15:0 vlan2 tag identifier (vti2) this field contains the vlan tag used to identify vlan2 frames. this field is compared with the 13th and 14th bytes of the incoming frames for vlan2 frame detection. note: if used, this register is typically set to the standard vlan value of 8100h. if both vlan1 and vlan2 tag identifiers are used, they should be unique. if both are set to the same value, vlan1 is given higher precedence and the maximum legal frame length is set to 1522. r/w ffffh downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 205 lan9250 11.15.11 host mac wake-up fram e filter register (hmac_wuff) this write-only register is used to configure the wake-up frame filter. refer to section 11.6.3, "wake-up frame detec- tion," on page 145 for additional information. offset: 0bh size: 32 bits bits description type default 31:0 wake-up frame filter (wff) the wake-up frame filter is configured through this register using an indexing mechanism. after power-on reset, digital reset, or host mac reset, the host mac loads the first value written to this location to the first dword in the wake-up frame filter (filter 0 byte ma sk 0). the second value written to this location is loaded to the second dword in the wake-up frame filter (filter 0 byte mask 1) and so on. once all 40 dwords have been written, the inter- nal pointer will once again point to the fi rst entry and the fi lter entries can be modified in the same manner. similarly, 40 dwords can be read sequen- tially to obtain the values stored in the wff. please refer to section 11.6.3, "wake-up frame detection," on page 145 for further information. note: this register should be read and written using 40 consecutive dword operations. failure to read or write the ent ire contents of the wff may cause the internal read/ write pointers to be left in a position other than pointing to the first entry. a mechanism for resetting the internal pointers to the beginning of the wff is available via the wff pointer reset (wff_ptr_rst) bit of the host mac wake-up control and status register (hmac_wucsr) . this mechanism enables the application program to re-synchronize with the internal wff pointers if it has not previously read/written the complete contents of the wff. r/w - downloaded from: http:///
lan9250 ds00001913a-page 206 ? 2015 microchip technology inc. 11.15.12 host mac wake-up control and status register (hmac_wucsr) this read/write register contains data and control settings pertaining to the host macs remote wake-up status and capabilities. it is used in conjunction with the host mac wake-up frame filter register (hmac_wuff) to fully configure the wake-up frame filter. refer to section 11.6.3, "wake-up frame detection," on page 145 for additional information. offset: 0ch size: 32 bits bits description type default 31 wff pointer reset (wff_ptr_rst) this self-clearing bit resets the wakeup frame filter (wff) internal read and write pointers to the beginning of the wff. sc 0b 30:10 reserved ro - 9 global unicast enable (gue) when set, the host mac wakes up from power-saving mode on receipt of a global unicast frame. this is accompli shed by enabling global unicasts as a wakeup frame qualifier. a global unicast frame has the mac address [0] bits set to 0. note: the wake-up frame enable (wuen) bit of this register must also be set to enable wakeup. r/w 0b 8 wol wait for slee p (wol_wait_sleep) when set, the wol functions are not ac tive until the device has entered a sleep state. when clear, wol functions are active immediately. r/w 0b 7 perfect da frame received (pfda_fr) the mac sets this bit upon receiving a valid frame with a destination address that matches the physical address. r/wc 0b 6 remote wake-up frame received (wufr) the host mac sets this bit upon receiving a valid remote wake-up frame. r/wc 0b 5 magic packet received (mpr) the host mac sets this bit upon receiving a valid magic packet r/wc 0b 4 broadcast frame received (bcast_fr) the mac sets this bit upon receiving a valid broadcast frame. r/wc 0b 3 perfect da wakeup enable (pfda_en) when set, remote wakeup mode is enabled and the mac is capable of wak- ing up on receipt of a frame with a de stination address that matches the physical address of the device. the physical address is stored in the host mac address high register (hmac_addrh) and host mac address low register (hmac_addrl) . r/w 0b 2 wake-up frame enable (wuen) when set, remote wake-up mode is enabled and the host mac is capable of detecting wake-up frames as programmed in the host mac wake-up frame filter register (hmac_wuff) . r/w 0b 1 magic packet enable (mpen) when set, magic packet wake-up mode is enabled. r/w 0b 0 broadcast wakeup enable (bcst_en) when set, remote wakeup mode is enabled and the mac is capable of wak- ing up from a broadcast frame. r/w 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 207 lan9250 11.15.13 host mac checksum offload en gine control register (hmac_coe_cr) this register controls the rx and tx checksum offload engines . offset: 0dh size: 32 bits bits description type default 31:17 reserved ro - 16 tx checksum offload engine enable (tx_coe_en) tx_coe_en may only be changed if the tx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the host mac is disabled and the tli is empty. 0 = the txcoe is bypassed 1 = the txcoe is enabled r/w 0b 15:2 reserved ro - 1 rx checksum offload engi ne mode (rx_coe_mode) this register indicates whether the co e will check for vlan tags or a snap header prior to beginning it s checksum calculation. in its default mode, the calculation will always begin 14 bytes into the frame. rx_coe_mode may only be changed if the rx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the host mac is disabled and the tli is empty. 0 = begin checksum calculation after first 14 bytes of ethernet frame 1 = begin checksum calculation at start of l3 packet by adjusting for vlan tags and/or snap header. r/w 0b 0 rx checksum offload engi ne enable (rx_coe_en) rx_coe_en may only be changed if the rx path is disabled. if it is desired to change this value during run time, it is safe to do so only after the host mac is disabled and the tli is empty. 0 = the rxcoe is bypassed 1 = the rxcoe is enabled r/w 0b downloaded from: http:///
lan9250 ds00001913a-page 208 ? 2015 microchip technology inc. 11.15.14 host mac eee time wait tx system register (hmac_eee_tw_tx_sys) this register configures the time to wait before starting packet transmission after tx lpi removal. offset: 0eh size: 32 bits bits description type default 31:24 reserved ro - 23:0 tx delay after tx lpi removal this field configures the time to wai t, in us, before starting packet transmis- sion after tx lpi removal. software should only change this field when the host mac energy efficient ethernet (hmac_eee_enable) bit is cleared. note: in order to meet the ieee 802.3 specified requirement, the minimum value of this field should be 00001eh. r/w 00001eh downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 209 lan9250 11.15.15 host mac eee tx lpi request de lay register (hmac_eee_tx_lpi_req_delay) this register contains the amount of ti me, in microseconds, the host mac must wait after the tx fifo is empty before invoking the lpi protocol. note: the actual time can be up to 1 us longer than specified. note: a value of zero is valid and will cause no delay to occur. note: if the tx fifo becomes non-em pty, the timer is restarted offset: 0fh size: 32 bits bits description type default 31:0 eee tx lpi request delay this field contains the time to wait, in microseconds, before invoking the lpi protocol. software should only change this field when the host mac energy efficient ethernet (hmac_eee_enable) bit is cleared. r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 210 ? 2015 microchip technology inc. 12.0 ethernet phy 12.1 functional overview the device contains a phy which connects to the host mac. the phy complies with the ieee 802.3 physical layer for twis ted pair ethernet and can be configured for full/half duplex 100 mbps (100base-tx / 100base-fx) or 10 mbps (10base-t) etherne t operation. all phy registers follow the ieee 802.3 (clause 22.2.4) sp ecified mii management register set and are fully configurable. 12.1.1 phy addressing the default address for the phy is fixed to 1. in addition, the address for the phy can be changed via the phy address (phyadd) field in the phy special modes register (phy_special_modes) . 12.2 phy the device integrates two ieee 802. 3 phy functions. the phy can be conf igured for either 100 mbps copper (100base-tx), 100 mbps fiber (100base-fx) or 10 mbps c opper (10base-t) ethernet operation and includes auto- negotiation and hp auto-mdix. 12.2.1 functional description functionally, the phy can be divided into the following sections: 100base-tx transmit and 100base-tx receive 10base-t transmit and 10base-t receive auto-negotiation hp auto-mdix phy management control and phy interrupts phy power-down modes and energy efficient ethernet resets link integrity test cable diagnostics loopback operation 100base-fx far end fault indication downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 211 lan9250 a block diagram of the main components of the phy can be seen in figure 12-1 . 12.2.2 100base-tx transmit the 100base-tx transmit data path is shown in figure 12-2 . shaded blocks are those which are internal to the phy. each major block is explained in the following sections. 12.2.2.1 100base-tx transmit data ac ross the internal mii interface for a transmission, the host mac drives the transmit data onto the internal mii txd bus and asserts the internal mii txen to indicate valid data. the data is in the form of 4-bit wide 25 mhz data. figure 12-1: phy block diagram figure 12-2: 100base-tx transmit data path hp auto-mdix txpa/txna rxpa/rxna to external ethernet pins 10/100 transmitter 10/100 reciever mii mac interface mii mdio auto- negotiation to host mac to host mac pll phy management control registers from system clocks controller interrupts to system interrupt controller port x mac 100m tx driver mlt-3 converter nrzi converter 4b/5b encoder magnetics cat-5 rj45 100m pll internal mii 25 mhz by 4 bits internal mii transmit clock 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 mlt-3 scrambler and piso 125 mbps serial mii mac interface 25mhz by 4 bits downloaded from: http:///
lan9250 ds00001913a-page 212 ? 2015 microchip technology inc. 12.2.2.2 4b/5b encoder the transmit data passes from the mii block to the 4b/5b enc oder. this block encodes the data from 4-bit nibbles to 5- bit symbols (known as code-groups) according to table 12-1 . each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. the remaining 16 code-groups are either used for control information or are not valid. the first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through f. the remaining code-groups are given letter designations with slashe s on either side. for example, an idle code-group is / i/, a transmit error code-group is /h/, etc. table 12-1: 4b/5b code table code group sym receiver interpreta tion transmitter interpretation 11110 0 0 0000 data 0 0000 data 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 a a 1010 a 1010 10111 b b 1011 b 1011 11010 c c 1100 c 1100 11011 d d 1101 d 1101 11100 e e 1110 e 1110 11101 f f 1111 f 1111 11111 /i/ idle sent after /t/r/ until the mii transmitter enable signal (txen) is received 11000 /j/ first nibble of ssd, translated to 0101 following idle, else mii receive error (rxer) sent for rising mii transmitter enable signal (txen) 10001 /k/ second nibble of ssd, translated to 0101 following j, el se mii receive error (rxer) sent for rising mii transmitter enable signal (txen) 01101 /t/ first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of mii receive error (rxer) sent for falling mii transmitter enable signal (txen) 00111 /r/ second nibble of esd, causes de-asser- tion of crs if following /t/, else assertion of mii receive error (rxer) sent for falling mii transmitter enable signal (txen) 00100 /h/ transmit error symbol sent fo r rising mii transmit error (txer) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 213 lan9250 12.2.2.3 scrambler and piso repeated data patterns (especially the idle code-group) ca n have power spectral densities with large narrow-band peaks. scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is required by fcc regulations to prevent excessive emi from being radiated by the physical wiring. the seed for the scrambler is generated from the phy addr ess, ensuring that each phy will have its own scrambler sequence. for more information on phy addressing, refer to section 12.1.1, "phy addressing" . the scrambler also performs the parallel in serial out conversion (piso) of the data. 12.2.2.4 nrzi and mlt-3 encoding the scrambler block passes the 5-bit wide parallel data to t he nrzi converter where it becomes a serial 125mhz nrzi data stream. the nrzi is then encoded to mlt-3. mlt-3 is a tri-level code where a change in the logic level represents a code bit 1 and the logic output remaining at the same level represents a code bit 0. 12.2.2.5 100m transmit driver the mlt-3 data is then passed to the analog transmitter, which drives the differential mlt-3 signal on output pins txpx and txnx, to the twisted pair media across a 1:1 ratio isolation transformer. the 10 base-t and 100base-tx signals pass through the same transformer so that common magnetics can be used for both. the transmitter drives into the 100 ? impedance of the cat-5 cable. cable termination and impedance matching require external components. 12.2.2.6 100m phase lock loop (pll) the 100m pll locks onto the reference clock and generates the 125 mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. 00110 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 11001 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 00000 /p/ sleep, indicates to receiver that the transmitter will be going to lpi sent due to lpi. used to tell receiver before transmitter goes to lpi. also used for refresh cycles during lpi. 00001 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 00010 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 00011 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 00101 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 01000 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid 01100 /v/ invalid, mii re ceive error (rxer) if during mii receive data valid (rxdv) invalid 10000 /v/ invalid, mii receive error (rxer) if during mii receive data valid (rxdv) invalid table 12-1: 4b/5b code table (continued) code group sym receiver interpreta tion transmitter interpretation downloaded from: http:///
lan9250 ds00001913a-page 214 ? 2015 microchip technology inc. 12.2.3 100base-tx receive the 100base-tx receive data path is shown in figure 12-3 . shaded blocks are those which are internal to the phy. each major block is explained in the following sections. 12.2.3.1 100m receive input the mlt-3 data from the cable is fed into the phy on inputs rxpx and rxnx via a 1:1 ratio transformer. the adc sam- ples the incoming differential signal at a rate of 125m sa mples per second. using a 64-level quantizer, 6 digital bits are generated to represent each sample. the dsp adjusts the gain of the adc according to the observed signal levels such that the full dynamic range of the adc can be used. 12.2.3.2 equalizer, blw correcti on and clock/data recovery the 6 bits from the adc are fed into the dsp block. the equ alizer in the dsp section compensates for phase and ampli- tude distortion caused by the physical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good-qua lity cat-5 cable between 1m and 100m. if the dc content of t he signal is such that the low-frequency comp onents fall below the low frequency pole of the iso- lation transformer, then the droop characteristics of the transformer will become significant and baseline wander (blw) on the received signal will result. to prevent corruption of the received data, the phy corrects for blw and can receive the ansi x3.263-1995 fddi tp-pmd defined killer packet with no bit errors. the 100m pll generates multiple phases of the 125mhz clock. a multip lexer, controlled by the timing unit of the dsp, selects the optimum phase for sampling the data. this is used as the received recovered clock. this clock is used to extract the serial data from the received signal. 12.2.3.3 nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered le vels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. 12.2.3.4 descrambler the descrambler performs an inverse function to the scrambler in the transmitter and also performs the serial in parallel out (sipo) conversion of the data. figure 12-3: 100base-tx receive data path port x mac a/d converter mlt-3 converter nrzi converter 4b/5b decoder magnetics cat-5 rj45 100m pll internal mii 25mhz by 4 bits internal mii receive clock 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 6 bit data descrambler and sipo 125 mbps serial dsp: timing recovery, equalizer and blw correction mlt-3 mii mac interface 25mhz by 4 bits downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 215 lan9250 during reception of idle (/i/) symbols. the descrambler synchronizes its descram bler key to the incoming stream. once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. special logic in the descrambler ensures synchronization wi th the remote transceiver by searching for idle symbols within a window of 4000 bytes (40 us). this window ensures that a maximum packet size of 1514 bytes, allowed by the ieee 802.3 standard, can be received wi th no interference. if no idle-symbols are detected within this time-period, receive operation is aborted and the descram bler re-starts the synchronization process. the de-scrambled signal is then aligned into 5-bit code-grou ps by recognizing the /j/k/ st art-of-stream delimiter (ssd) pair at the start of a packet. once the code-word alignment is determined, it is stored and utilized until the next start of frame. 12.2.3.5 5b/4b decoding the 5-bit code-groups are translated into 4-bit data nibbles according to the 4b/5b table. the translated data is pre- sented on the internal mii rxd[3:0] signal lines. the ssd, /j/k/, is translated to 0101 0101 as the first 2 nibbles of the mac preamble. reception of the ssd causes the transceiver to assert the receive data valid signal, indicating that valid data is available on the rxd bus. successive valid code-groups are translated to data nibbles. reception of either the end of stream delimiter (esd) consisting of the /t/r/ symbols , or at least two /i/ symbols causes the transceiver to de- assert carrier sense and receive data valid signal. 12.2.3.6 receive data valid signal the internal miis receive data valid signal (rxdv) indicates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rxclk. rxdv becom es active after the /j/k/ delimiter has been recognized and rxd is aligned to nibble boundaries. it remains active until either the /t/r/ delimiter is recognized or link test indi- cates failure or sigdet becomes false. rxdv is asserted when the first nibble of translated /j/k/ is ready for trans fer over the media independent interface. 12.2.3.7 receiver errors during a frame, unexpected code-groups are considered re ceive errors. expected code groups are the data set (0 through f), and the /t/r/ (esd) symbol pair. when a receive error occurs, the internal miis rxer signal is asserted and arbitrary data is driven onto the internal miis rxd[3:0] lines. should an error be detected during the time that the / j/k/ delimiter is being decoded (bad ssd error), rxer is as serted true and the value 11 10b is driven onto the rxd[3:0] lines. note that the internal miis data valid signal (rxdv) is not yet assert ed when the bad ssd occurs. 12.2.3.8 100m receive data acro ss the internal mii interface for reception, the 4-bit data nibbles are sent to the mii ma c interface block. these data nibbles are clocked to the con- troller at a rate of 25 mhz. rxclk is the output clock for the internal mii bus. it is recovered from the received data to clock the rxd bus. if there is no received signal, it is derived from the system reference clock. 12.2.4 10base-t transmit the 10base-t transmitter receives 4-bit nibbles from th e internal mii at a rate of 2. 5 mhz and converts them to a 10 mbps serial data stream. the data stream is then mancheste r-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. 10base-t transmissions use the following blocks: mii (digital) tx 10m (digital) 10m transmitter (analog) 10m pll (analog) 12.2.4.1 10m transmit data acro ss the internal mii interface for a transmission, the host mac drives the transmit data onto the internal mii txd bus and asserts the internal mii txen to indicate valid data. the data is in the form of 4-bit wide 2.5 mhz data. in half-duplex mode the transceiver loops back the transmitte d data, on the receive path. this does not confuse the mac/controller since the col signal is not asserted during th is time. the transceiver also supports the sqe (heartbeat) signal. note: these symbols are not translated into data. downloaded from: http:///
lan9250 ds00001913a-page 216 ? 2015 microchip technology inc. 12.2.4.2 manchester encoding the 4-bit wide data is sent to the 10m tx block. the nibbles are converted to a 10mbps serial nrzi data stream. the 10m pll produces a 20mhz clock. this is used to ma nchester encode the nrz data stream. when no data is being transmitted (internal mii txen is low), the 10m tx driver block outputs normal link pulses (nlps) to maintain commu- nications with the remote link partner. 12.2.4.3 10m transmit drivers the manchester encoded data is sent to the analog tran smitter where it is shaped a nd filtered before being driven out as a differential signal acro ss the txpx and txnx outputs. 12.2.5 10base-t receive the 10base-t receiver gets the manchester-encoded analog si gnal from the cable via the magnetics. it recovers the receive clock from the signal and uses this clock to recover the nrzi data stream. this 10m serial data is converted to 4-bit data nibbles which are passed to the controller across the internal mii at a rate of 2.5mhz. 10base-t reception uses the following blocks: filter and squelch (analog) 10m pll (analog) rx 10m (digital) mii (digital) 12.2.5.1 10m receive input and squelch the manchester signal from the cable is fed into the transceiver (on inputs rxpx and rxnx) via 1:1 ratio magnetics. it is first filtered to reduce any out-of -band noise. it then passes through a sq uelch circuit. the squelch is a set of amplitude and timing comparators that norm ally reject differential voltage levels below 300mv and detect and recognize differential voltages above 585mv. 12.2.5.2 manchester decoding the output of the squelch goes to the 10m rx block where it is validated as manchester encoded data. the polarity of the signal is also checked. if the pol arity is reversed (local rxp is connected to rxn of the remote partner and vice versa), the condition is identified and corrected . the reversed condition is indicated by the 10base-t polarity state (xpol) bit in phy special control/status indication register (phy_specia l_control_stat_ind) . the 10m pll is locked onto the received manchester signal, from which t he 20mhz clock is generated. using this clock, the man- chester encoded data is extracted and converted to a 10mhz nr zi data stream. it is then converted from serial to 4-bit wide parallel data. the rx10m block also detects valid 10 base-t idle signals - normal link puls es (nlps) - to maintain the link. 12.2.5.3 10m receive data across the internal mii interface for reception, the 4-bit data nibbles are sent to the mii mac interface block. these data nibbles are clocked to the con- troller at a rate of 2.5 mhz. 12.2.5.4 jabber detection jabber is a condition in which a station transmits for a peri od of time longer than the maximum permissible packet length, usually due to a fault condition, which results in holding the internal mii txen input for a long period. special logic is used to detect the jabber state and abort the transmission to the line, within 45 ms. once txen is deasserted, the logic resets the jabber condition. the jabber detect bit in the phy basic status register (phy_basic_status) indicates that a jabber condition was detected. 12.2.6 auto-negotiation the purpose of the auto-negotiation func tion is to automatically configure the transceiver to the optimum link parame- ters based on the capabilities of its link partner. auto-nego tiation is a mechanism for exchanging configuration informa- tion between two link-partners and automatically selectin g the highest performance mode of operation supported by both sides. auto-negotiation is fully defined in clause 28 of the ieee 802.3 spec ification and is enabled by setting the auto-negotiation enable (phy_an) of the phy basic control regist er (phy_basic_control) . downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 217 lan9250 the advertised capabilities of the phy are stored in the phy auto-negotiation advertisem ent register (phy_an_adv) . the phy contains the ability to advertise 100base-tx and 10base-t in both full or half-duplex modes. besides the connection speed, the phy can advertise remote fault indi cation and symmetric or asymmetric pause flow control as defined in the ieee 802.3 specification. the transceiver s upports next page capability which is used to negotiate energy efficient ethernet functionality as well as to sup port software controlled pages. many of the default advertised capabilities of the phy are determined via configuration straps as shown in section 12.2.18.5, "phy auto-negotiation advertisement register (phy_an_adv)," on page 238 . refer to section 7.0, "configuration straps," on page 54 for additional details on how to use the device configuration straps. once auto-negotiation has completed, information about the resolved link and the results of the negotiation process are reflected in the speed indication bits in the phy special control/status register (phy_special_control_sta- tus) , as well as the phy auto-negotiation link partner base pa ge ability register (phy_an_lp_base_ability) . the auto-negotiation protocol is a purely physical layer activity and proceeds independ ently of the mac controller. the following blocks are activated during an auto-negotiation session: auto-negotiation (digital) 100m adc (analog) 100m pll (analog) 100m equalizer/blw/clock recovery (dsp) 10m squelch (analog) 10m pll (analog) 10m transmitter (analog) when enabled, auto-negotiation is started by the occurrence of any of the following events: power-on reset (por) hardware reset (rst#) phy software reset (via reset control register (reset_ctl) , or bit 15 of the phy basic control register (phy_basic_control) ) phy power-down reset ( section 12.2.10, "phy power-down modes," on page 222 ) phy link status down (bit 2 of the phy basic status register (phy_basic_status) is cleared) setting the phy basic control regist er (phy_basic_control) , bit 9 high (auto-neg restart) digital reset (via bit 0 of the reset control register (reset_ctl) ) issuing an eeprom loade r reload command ( section 13.4, "eeprom loader," on page 290 ) via eeprom loader run sequence on detection of one of these ev ents, the transceiver begins auto-negotiation by transmitting bursts of fast link pulses (flp). these are bursts of link pulses from the 10m tx driver. they are s haped as normal link pulses and can pass uncorrupted down cat-3 or cat-5 cable. a fast link pulse burst consists of up to 33 pulses. the 17 odd-numbered pulses, which are always present, frame the flp burst. the 16 even-numbered pu lses, which may be present or absent, contain the data word being transmitted. presence of a dat a pulse represents a 1, while absence represents a 0. the data transmitted by an flp burst is known as a link code word. these are defined fully in ieee 802.3 clause 28. in summary, the transceiver advertises 802.3 compliance in its se lector field (the first 5 bits of the link code word). it advertises its technology ability according to the bits set in the phy auto-negotiation advertisement register (phy_an_adv) . there are 4 possible matches of the technology abilities. in the order of priority these are: 100m full duplex (highest priority) 100m half duplex 10m full duplex 10m half duplex (lowest priority) note: auto-negotiation is not used for 100base-fx mode. note: refer to section 6.2, "resets," on page 38 for information on these and other system resets. downloaded from: http:///
lan9250 ds00001913a-page 218 ? 2015 microchip technology inc. if the full capabilities of the transceiver are advertised (100m, full-duplex), and if the link partner is capable of 10m and 100m, then auto-negotiation selects 100m as the highest pe rformance mode. if the link partner is capable of half and full-duplex modes, then auto-negotiation sele cts full-duplex as the highest performance mode. once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any dif- ference in the main content of the link code words at this time will caus e auto-negotiation to re-start. auto-negotiation will also re-start if not all of the required flp bursts are received. writing the phy auto-negotiation advertisement register (phy_an_adv) bits [8:5] allows software control of the capa- bilities advertised by the transceiver. writing the phy auto-negotiation advertisement register (phy_an_adv) does not automatically re-start auto-negotiation. the restart auto-negotiation (phy_rst_an) bit of the phy basic control register (phy_basic_control) must be set before the new abilities wi ll be advertised. auto-negotiation can also be disabled via software by clearing the auto-negotiation enable (phy_an) bit of the phy basic control register (phy_basic_control) . 12.2.6.1 pause flow control the host mac is capable of generating and receiving pause fl ow control frames per the ie ee 802.3 specification. the phys advertised pause flow control abilities are set via the asymmetric pause and symmetric pause bits of the phy auto-negotiation advertisement register (phy_an_adv) . this allows the phy to advertise its flow control abilities and auto-negotiate the flow control settings with its link partner . the default values of these bits are determined via config- uration straps as defined in section 12.2.18.5, "phy auto -negotiation advertisement register (phy_an_adv)," on page 238 . 12.2.6.2 parallel detection if the device is connected to a device lacking the ability to au to-negotiate (i.e. no flps are de tected), it is able to deter- mine the speed of the link based on either 100m mlt-3 symbol s or 10m normal link pulses. in this case the link is presumed to be half-duplex per the ieee 802.3 standard. this ability is known as paralle l detection. this feature ensures interoperability with legacy link partners. if a link is formed via parallel detection, then the link partner auto- negotiation able bit of the phy auto-negotiation expansion register (phy_an_exp) is cleared to indicate that the link partner is not capable of auto-negotiation. if a fault occurs during parallel detection, the parallel detection fault bit of the phy auto-negotiation expansion register (phy_an_exp) is set. the phy auto-negotiation link partner base p age ability register (phy_an_lp_base_ability) is used to store the link partner ability information, which is coded in the receiv ed flps. if the link partner is not auto-negotiation capable, then this register is updated after completion of parallel detec tion to reflect the speed capability of the link partner. 12.2.6.3 restarting auto-negotiation auto-negotiation can be re-started at any time by setting the restart auto-negotiation (phy_rst_an) bit of the phy basic control register (phy_basic_control) . auto-negotiation will also re-start if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto-negotiation resume s in an attempt to determine the new link configuration. if the management entity re-starts auto-negotiation by setting the restart auto-negotiation (phy_rst_an) bit of the phy basic control regist er (phy_basic_control) , the device will respond by stopping all transmission/receiving operations. once the internal break_link_time is comple ted in the auto-negotiation state-machine (approximately 1200ms), auto-negotiation will re-start. in this case, the li nk partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation. auto-negotiation is also restarted afte r the eeprom loader updates the straps. 12.2.6.4 disabling auto-negotiation auto-negotiation can be disabled by clearing the auto-negotiation enable (phy_an) bit of the phy basic control reg- ister (phy_basic_control) . the transceiver will then force its speed of operation to reflect the information in the phy basic control regist er (phy_basic_control) ( speed select lsb (phy_speed_sel_lsb) and duplex mode (phy_duplex) ). these bits are ignored when auto-negotiation is enabled. 12.2.6.5 half vs. full-duplex half-duplex operation relies on the csma/ cd (carrier sense multiple access / collision detect) protocol to handle net- work traffic and collisions. in this mode , the carrier sense signal, crs, responds to both transmit and receive activity. if data is received while the transceiver is transmitting, a collision results. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 219 lan9250 in full-duplex mode, the transceiver is able to transmit and receive data simultaneously. in this mode, crs responds only to receive activity. the csma/cd protocol does not apply and collision detection is disabled. 12.2.7 hp auto-mdix hp auto-mdix facilitates the use of cat-3 (10 base-t) or cat-5 (100 base-t) media utp interconnect cable without consideration of interface wiring scheme. if a user plugs in either a direct connect lan cable or a cross-over patch cable, as shown in figure 12-4 , the transceiver is capable of configuring the txpx/txnx and rxpx/rxnx twisted pair pins for correct transceiver operation. the internal logic of the device detects the tx and rx pi ns of the connecting device. si nce the rx and tx line pairs are interchangeable, special pcb design considerations are needed to accommodate the symmetrical magnetics and termination of an auto-mdix design. the auto-mdix function is enabled using the auto_mdix_strap_1 configuration strap. manual selection of the cross-over can be set using the manual_mdix_strap_1 configuration strap. software bas ed control of the auto -mdix function may be performed using the auto-mdix control (amdixctrl) bit of the phy special control/status indication register (phy_special_control_stat_ind) . when amdixctrl is set to 1, the auto-mdix capability is determined by the auto-mdix enable (amdixen) and auto-mdix state (amdixstate) bits of the phy special control/status indication register (phy_special_control_stat_ind) . 12.2.8 phy management control the phy management control block is responsible for the m anagement functions of the phy, including register access and interrupt generation. a serial manag ement interface (smi) is used to support registers as required by the ieee 802.3 (clause 22), as well as the vendor specific registers allowed by the specificat ion. the smi interface consists of note: auto-mdix is not used for 100base-fx mode. note: when operating in 10base-t or 100base-tx manual modes, the auto -mdix crossover time can be extended via the extend manual 10/100 auto-mdix crossover time bit of the phyedpd nlp / crossover time / eee configuration register (phy_edpd_cfg) . refer to section 12.2.18.12, on page 247 for addi- tional information. when energy detect power-down is enabled, the au to-mdix crossover time can be extended via the edpd extend crossover bit of the phyedpd nlp / crossover time / eee configuration register (phy_edpd_cfg) . refer to section 12.2.18.12, on page 247 for additional information figure 12-4: direct cable connection vs. cross-over cable connection 12 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used 12 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used direct connect cable rj-45 8-pin straight-through for 10base-t/100base-tx signaling 12 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used 12 3 4 5 6 7 8 txpx txnx rxpx not used not used rxnx not used not used cross-over cable rj-45 8-pin cross-over for 10base-t/100base-tx signaling downloaded from: http:///
lan9250 ds00001913a-page 220 ? 2015 microchip technology inc. the mii management data (mdio) signal and the mii manag ement clock (mdc) signal. these signals allow access to all phy registers. refer to section 12.2.18, "phy registers," on page 230 for a list of all supported registers and register descriptions. non-supported r egisters will be read as ffffh. 12.2.9 phy interrupts the phy contains the ability to generat e various interrupt events. reading the phy interrupt source flags register (phy_interrupt_source) shows the source of the interrupt. the phy interrupt mask register (phy_inter- rupt_mask) enables or disables each phy interrupt. the phy management control block aggregates the enabled inte rrupts status into an internal signal which is sent to the system interrupt controller and is reflected via the phy interrupt event (phy_int) bit of the interrupt status reg- ister (int_sts) . for more information on the device in terrupts, refer to section 8.0, "system interrupts," on page 62 . the phy interrupt system provides two modes, a primary interrupt mode and an alternative interrupt mode. both modes will assert the internal interrupt signal sent to the system interrupt controller when the corresponding mask bit is set. these modes differ only in how they de-assert the internal interrupt signal. these modes are detailed in the following subsections. 12.2.9.1 primary interrupt mode the primary interrupt mode is the default interrupt mode. t he primary interrupt mode is always selected after power-up or hard reset. in this mode, to enable an interrupt, set the corresponding mask bit in the phy interrupt mask register (phy_interrupt_mask) (see table 12-2 ). when the event to assert an interrupt is true, the internal interrupt signal will be asserted. when the corresponding event to de-assert the interrupt is true, the internal interrupt signal will be de- asserted. note: the primary interrupt mode is the default interrupt mode after a power-up or hard reset. the alternative interrupt mode requires setup after a power-up or hard reset. table 12-2: interrupt management table mask interrupt source flag interrupt source event to assert interrupt event to de-assert interrupt 30.9 29.9 link up linkstat see note 1 link status rising link- stat falling linksat or reading register 29 30.7 29.7 energyon 17.1 energyon rising 17.1 ( note 3 ) falling 17.1 or reading register 29 30.6 29.6 auto-negotia- tion complete 1.5 auto-negoti- ate com- plete rising 1.5 falling 1.5 or reading register 29 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 221 lan9250 note 1: linkstat is the internal link status and is not directly available in any register bit. note 2: if the mask bit is enabled and the internal interrupt signal has been de-asserted while energyon is still high, the internal interrupt signal will assert for 256 ms, approximately one second after energyon goes low when the cable is unplugged. to prevent an unexpected assertion of the internal interrupt signal, the energyon interrupt mask should always be cleared as part of the energyon interrupt service routine. 12.2.9.2 alternat e interrupt mode the alternate interrupt mode is enabled by setting the altint bit of the phy mode control/stat us register (phy_- mode_control_status) to 1. in this mode, to enable an interrupt, set the corresponding bit of the in the phy interrupt mask register (phy_interrupt_mask) (see table 12-3 ). to clear an interrupt, clear the interrupt source and write a 1 to the corresponding interrupt source flag. wr iting a 1 to the interrupt source flag will cause the state machine to check the interrupt source to determine if the inte rrupt source flag should clear or stay as a 1. if the con- 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 falling 1.4, or reading register 1 or reading register 29 30.4 29.4 link down 1.2 link status falling 1.2 reading register 1 or reading register 29 30.3 29.3 auto-negotia- tion lp acknowl- edge 5.14 acknowl- edge rising 5.14 falling 5.14 or reading register 29 30.2 29.2 parallel detec- tion fault 6.4 parallel detection fault rising 6.4 falling 6.4 or reading register 6, or reading register 29, or re-auto negotiate or link down 30.1 29.1 auto-negotia- tion page received 6.1 page received rising 6.1 falling 6.1 or reading register 6, or reading register 29, or re-auto negotiate, or link down. note: the energy on (energyon) bit in the phy mode control/status register (phy_mode_con- trol_status) is defaulted to a 1 at the start of the signal acquisition process, therefore the int7 bit in the phy interrupt source flags r egister (phy_interrupt_source) will also read as a 1 at power- up. if no signal is present, then both energy on (energyon) and int7 will clear within a few milliseconds. table 12-2: interrupt management table (continued) downloaded from: http:///
lan9250 ds00001913a-page 222 ? 2015 microchip technology inc. dition to de-assert is true, th en the interrupt source flag is cleared and the internal interrupt signal is also deasserted. if the condition to de-assert is false, then the interrupt source flag remains set, and the internal interrupt signal remains asserted. note 3: linkstat is the internal link status and is not directly available in any register bit. 12.2.10 phy power-down modes there are two phy power-down modes: general power-down mode and energy detect power-down mode. these modes are described in the following subsections. table 12-3: alternative interrupt mode management table mask interrupt source flag interrupt source event to assert interrupt condition to de-assert bit to clear interrupt 30.9 29.9 link up linkstat see note 3 link status rising link- stat linkstat low 29.9 30.7 29.7 energyon 17.1 energyon rising 17.1 17.1 low 29.7 30.6 29.6 auto-negotia- tion complete 1.5 auto-negoti- ate com- plete rising 1.5 1.5 low 29.6 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 1.4 low 29.5 30.4 29.4 link down 1.2 link status falling 1.2 1.2 high 29.4 30.3 29.3 auto-negotia- tion lp acknowl- edge 5.14 acknowl- edge rising 5.14 5.14 low 29.3 30.2 29.2 parallel detec- tion fault 6.4 parallel detection fault rising 6.4 6.4 low 29.2 30.1 29.1 auto-negotia- tion page received 6.1 page received rising 6.1 6.1 low 29.1 note: the energy on (energyon) bit in the phy mode control/status register (phy_mode_con- trol_status) is defaulted to a 1 at the start of the signal acquisition process, therefore the int7 bit in the phy interrupt source flags r egister (phy_interrupt_source) will also read as a 1 at power- up. if no signal is present, then both energy on (energyon) and int7 will clear within a few milliseconds. note: for more information on the various power ma nagement features of the device, refer to section 6.3, "power management," on page 44 . the phy power-down modes do not reload or reset the phy registers. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 223 lan9250 12.2.10.1 general power-down this power-down mode is controlled by the power down (phy_pwr_dwn) bit of the phy basic control register (phy_basic_control) . in this mode the entire transceiver, except the phy management cont rol interface, is pow- ered down. the transceiver will remain in this power-down state as long as the power down (phy_pwr_dwn) bit is set. when the power down (phy_pwr_dwn) bit is cleared, the transceiver pow ers up and is automatically reset. 12.2.10.2 energy detect power-down this power-down mode is enabled by setting the energy detect power-down (edpwrdown) bit of the phy mode control/status register (phy_mode_control_status) . in this mode, when no energy is present on the line, the entire transceiver is powered down (exc ept for the phy management control inte rface, the squelch circuit and the energyon logic). the energyon logic is used to detect the presence of valid energy from 100base-tx, 10base- t, or auto-negotiation signals. in this mode, when the energy on (energyon) bit in the phy mode control/status register (phy_mode_con- trol_status) signal is low, the transceiver is powered down and nothing is transmitted. when energy is received, via link pulses or packets, the energy on (energyon) bit goes high, and the transceiver powers up. the transceiver automatically resets itself into the st ate prior to power-down, and asserts the int7 bit of the phy interrupt source flags register (phy_interrupt_source) . the first and possibly second packet to activate energyon may be lost. when the energy detect power-down (edpwrdown) bit of the phy mode control/status register (phy_mode_- control_status) is low, energy detect power-down is disabled. when in edpd mode, the devices nlp characteristics may be modified. the device can be configured to transmit nlps in edpd via the edpd tx nlp enable bit of the phyedpd nlp / crossover time / eee configuration register (phy_edpd_cfg) . when enabled, the tx nlp time interval is configurable via the edpd tx nlp interval timer select field of the phyedpd nlp / crossover time / eee co nfiguration regist er (phy_edpd_cfg) . when in edpd mode, the device can also be configured to wake on the recept ion of one or two nlps. setting the edpd rx single nlp wake enable bit of the phyedpd nlp / crossover time / eee configuration register (phy_edpd_cfg) will enable the device to wake on reception of a single nlp. if the edpd rx single nlp wake enable bit is cleared, the maximum interval for detecting reception of two nl ps to wake from edpd is configurable via the edpd rx nlp max interval detect select field of the phyedpd nlp / crossover time / eee c onfiguration regist er (phy_edpd_cfg) . the energy detect power down feature is part of the broad er power management features of the device and can be used to trigger the power manag ement event output pin ( pme ) or general interrupt request pin ( irq ). this is accomplished by enabling the energy detect power-dow n feature of the phy as described abov e, and setting the energy detect enable of the power management control register (pmt_ctrl) . refer to power management for additional information. 12.2.11 energy efficient ethernet the phy supports ieee 802.3az energy efficient ethernet (eee). the eee functionality is enabled/disabled via the phy energy efficient ethernet enable (phyeeeen) bit of the phyedpd nlp / crossover ti me / eee configuration register (phy_edpd_cfg) . energy efficient ethernet is enabled or disabled by default via the eee_enable_strap_1 configuration strap. in order for eee to be utilized, the following conditions must be met: eee functionality must be enabled via the phy energy efficient et hernet enable (phyeeeen) bit of the phy- edpd nlp / crossover time / eee conf iguration register (phy_edpd_cfg) the 100base-tx eee bit of the mmd phy eee advertisement register (phy_eee_adv) must be set the mac and link-partner must support and be configured for eee operation the device and link-partner must link in 100base-tx full-duplex mode the value of the phy energy efficient ethernet enable (phyeeeen) bit affects the default values of the following reg- ister bits: 100base-tx eee bit of the mmd phy eee capability register (phy_eee_cap) 100base-tx eee bit of the mmd phy eee advertisement register (phy_eee_adv) note: energy efficient ethernet is not used for 100base-fx mode. downloaded from: http:///
lan9250 ds00001913a-page 224 ? 2015 microchip technology inc. 12.2.12 resets in addition to the chip-level hardware reset ( rst# ) and power-on reset (p or), the phy supports three block specific resets. these are discussed in the following sections. for detailed information on all device resets and the reset sequence refer to section 6.2, "resets," on page 38 . 12.2.12.1 phy software reset via reset_ctl the phy can be reset via the reset control register (reset_ctl) . this bit is self clearing after approximately 102 us. this reset does not reload the configurat ion strap values into the phy registers. 12.2.12.2 phy software reset via phy_basic_ctrl the phy can also be reset by setting the soft reset (phy_srst) bit of the phy basic control register (phy_basic_- control) . this bit is self clearing and will return to 0 after t he reset is complete. this re set does not reload the con- figuration strap values into the phy registers. 12.2.12.3 phy power-down reset after the phy has returned from a power-down state, a re set of the phy is automatically generated. the phy power- down modes do not reload or reset the phy registers. refer to section 12.2.10, "phy power-down modes," on page 222 for additional information. 12.2.13 link integrity test the device performs the lin k integrity test as outlined in the ieee 802.3u (c lause 24-15) link moni tor state diagram. the link status is multiplexed with the 10 mbps link status to form the link status bit in the phy basic status register (phy_basic_status) and to drive the link led functions. the dsp indicates a valid mlt-3 waveform present on the rxpx and rxnx signals as defined by the ansi x3.263 tp- pmd standard, to the link monitor state-machine, us ing the internal data_valid signal. when data_valid is asserted, the control logic moves into a link-ready state and waits for an enable from the auto-negotiation block. when received, the link-up state is entered, and the transmit and receive logic blocks become active. should auto-negoti- ation be disabled, the link integrity logic moves immediat ely to the link-up state when the data_valid is asserted. to allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time data_valid is asserted until the link-ready state is entered. should the data_valid input be negat ed at any time, this logic will immediately negate the link signal and enter the link-down state. when the 10/100 digital blo ck is in 10base-t mode, the link status is derived from the 10base-t receiver logic. 12.2.14 cable diagnostics the phy provides cable diagnostics which allow for open/shor t and length detection of the ethernet cable. the cable diagnostics consist of two primary modes of operation: time domain reflectometry (tdr) cable diagnostics tdr cable diagnostics enable the detection of open or shor ted cabling on the tx or rx pair, as well as cable length estimation to the open/short fault. matched cable diagnostics matched cable diagnostics enable cable length estimation on 100 mbps-linked cables. refer to the following sub-sections for details on proper operation of each cable diagnostics mode. note: only a hardware reset ( rst# ) or power-on reset (por) will automatically reload the configuration strap values into the phy registers. the digital reset (digital_rst) bit in the reset control register (reset_ctl) does not reset the phy. the digital reset (digital_rst) bit will cause the eeprom loader to reload the configuration strap val- ues into the phy registers and to reset all other phy registers to their default values. an eeprom reload command via the eeprom command register (e2p_cmd) also has the same effect. for all other phy resets, phy registers will need to be manually configured via software. note: cable diagnostics are not used for 100base-fx mode. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 225 lan9250 12.2.14.1 time domain reflectometry (tdr) cable diagnostics the phy provides tdr cable diagnostics which enable the detecti on of open or shorted cabli ng on the tx or rx pair, as well as cable length estimation to the open/short faul t. to utilize the tdr cable diagnostics, auto-mdix and auto negotiation must be disabled, and the phy must be forced to 100 mbps full-duplex mode. these actions must be per- formed before setting the tdr enable bit in the phy tdr control/status register (phy_tdr_control_stat) . with auto-mdix disabled, the tdr will test the tx or rx pair selected by register bit 27.13 ( auto-mdix state (amdix- state) ). proper cable testing should include a test of each pair. tdr cable diagnostics is not ap propriate for 100base- fx mode. when tdr testing is complete, prior register settings may be restored. figure 12-5 provides a flow diagram of proper tdr usage. figure 12-5: tdr usage flow diagram disable amdix and force mdi (or mdix) write phy reg 27: 0x8000 (mdi) - or - write phy reg 27: 0xa000 (mdix) tdr channel status complete? disable aneg and force 100mb full- duplex write phy reg 0: 0x2100 enable tdr write phy reg 25: 0x8000 no reg 25.8 == 0 yes reg 25.8 == 1 check tdr control/status register read phy reg 25 save: tdr channel type (reg 25.10:9) tdr channel length (reg 25.7:0) mdix case tested? yes repeat testing in mdix mode done start downloaded from: http:///
lan9250 ds00001913a-page 226 ? 2015 microchip technology inc. the tdr operates by transmitting puls es on the selected twisted pair within the ethernet cable (tx in mdi mode, rx in mdix mode). if the pair being tested is open or shorted, the resulting impedance discontinuity results in a reflected signal that can be detected by the phy. the phy measures the time between the transmitted signal and received reflec- tion and indicates the results in the tdr channel length field of the phy tdr control/status register (phy_tdr_- control_stat) . the tdr channel length field indicates the electrical length of the cable, and can be multiplied by the appropriate propagation constant in ta b l e 1 2 - 4 to determine the approximate physical distance to the fault. since the tdr relies on the reflected si gnal of an improperly terminated cable, th ere are several factors that can affect the accuracy of the physical length estimate. these include: 1. cable type (cat 5, cat5e, cat6): the electrical length of each cable type is slightly different due to the twists- per-meter of the internal signal pairs and differences in signal propagation spee ds. if the cable type is known, the length estimate can be calculated more accurately by using the propagation constant appropriate for the cable type (see ta b l e 1 2 - 4 ). in many real-world applications the cable type is unknown, or may be a mix of different cable types and lengths. in this case, use the propagation constant for the unknown cable type. 2. tx and rx pair: for each cable type, the eia standards specify different twist rates (twists-per-meter) for each signal pair within the ethernet cable. this results in different measurements for the rx and tx pair. 3. actual cable length: the difference between the estimated cable le ngth and actual cable length grows as the physical cable length increases, with the most accurate results at less than approximately 100 m. 4. open/short case: the open and shorted cases will return diff erent tdr channel length values (electrical lengths) for the same physical distance to the fault. comp ensation for this is achieved by using different propa- gation constants to calculate the physical length of the cable. for the open case, the estimated distance to the fault can be calculated as follows: distance to open fault in meters ?? tdr channel length * p open where: p open is the propagation c onstant selected from table 12-4 for the shorted case, the estimated distance to the fault can be calculated as follows: distance to open fault in meters ? tdr channel length * p short where: p short is the propagation constant selected from table 12-4 the typical cable length measurement margin of error for open and shorted cases is dependent on the selected cable type and the distance of the open/short from the device. ta b l e 1 2 - 5 and ta b l e 1 2 - 6 detail the typical measurement error for open and shorted cases, respectively. note: the tdr function is typically used when the link is inoperable. however, an active link will drop when oper- ating the tdr. table 12-4: tdr propagation constants tdr propagation constant cable type unknown cat 6 cat 5e cat 5 p open 0.769 0.745 0.76 0.85 p short 0.793 0.759 0.788 0.873 table 12-5: typical measurement error for open cable (+/- meters) physical distance to fault selected propagation constant p open = unknown p open = cat 6 p open = cat 5e p open = cat 5 cat 6 cable, 0-100 m 96 cat 5e cable, 0-100 m 5 5 cat 5 cable, 0-100 m 13 3 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 227 lan9250 12.2.14.2 matched cable diagnostics matched cable diagnostics enable cable length estimation on 100 mbps-linked cables of up to 120 meters. if there is an active 100 mb link, the approximate distance to the link partner can be estimated using the phy cable length register (phy_cable_len) . if the cable is properly terminated, but there is no active 100 mb link (the link partner is disabled, nonfunctional, the link is at 10 mb, etc.), th e cable length cannot be estimated and the phy cable length register (phy_cable_len) should be ignored. the estimated distance to the link partner can be determined via the cable length (cbln) field of the phy cable length register (phy_cable_len) using the lookup table provided in table 12- 7 . the typical cable length measurement margin of error for a matched cable case is +/- 20 m. the matched cable length margin of error is consistent for all cable types from 0 to 120 m. cat 6 cable, 101-160 m 14 6 cat 5e cable, 101-160 m 8 6 cat 5 cable, 101-160 m 20 6 table 12-6: typical measurement error for shorted cable (+/- meters) physical distance to fault selected propagation constant p short = unknown p short = cat 6 p short = cat 5e p short = cat 5 cat 6 cable, 0-100 m 85 cat 5e cable, 0-100 m 5 5 cat 5 cable, 0-100 m 11 2 cat 6 cable, 101-160 m 14 6 cat 5e cable, 101-160 m 7 6 cat 5 cable, 101-160 m 11 3 table 12-7: match case estimated cable length (cbln) lookup cbln field value estimated cable length 0 - 3 0 4651 7 62 7 73 8 84 9 95 9 10 70 11 81 12 91 table 12-5: typical measurement error for open cable (+/- meters) downloaded from: http:///
lan9250 ds00001913a-page 228 ? 2015 microchip technology inc. 12.2.15 loopback operation the phy may be configured for near-end loopback and connector loopback. these loopback modes are detailed in the following subsections. 12.2.15.1 near-end loopback near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indi- cated by the blue arrows in figure 12-6 . the near-end loopback mode is enabled by setting the loopback (phy_loop- back) bit of the phy basic control regist er (phy_basic_control) to 1. a large percentage of the digital circuitry is operational in near-end loopback mode because data is routed through the pcs and pma layers into the pmd sub- layer before it is looped back. the col signal will be inactive in this mode, unless collision test mode (phy_col_test) is enabled in the phy basic control regist er (phy_basic_control) . the transmitters are pow- ered down regardless of the state of the internal mii txen signal. 13 102 14 113 15 123 note: for a properly terminated cable (match case), t here is no reflected signal. in this case, the tdr channel length field is invalid and should be ignored. figure 12-6: near-end loopback block diagram table 12-7: match case estimated cable length (cbln) lookup 10/100 ethernet mac cat-5 xfmr digital rxd txd analog rx tx xx downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 229 lan9250 12.2.15.2 connector loopback the device maintains reliable transmission over very short cables and can be tested in a connector loopback as shown in figure 12-7 . an rj45 loopback cable can be used to route the transmit signals from the output of the transformer back to the receiver inputs. the loopback works at both 10 and 100 mbps. 12.2.16 100base-fx operation when set for 100base-fx operati on, the scrambler and mtl-3 blocks are disable and the analog rx and tx pins are changed to differential lvpecl pins and connect through extern al terminations to the external fiber transceiver. the differential lvpecl pins support a signal voltage range compatible with sff (lvpecl) and sfp (reduced lvpecl) type transceivers. while in 100base-fx operation, the quality of the receive sign al is provided by the exter nal transceiver as either an open-drain, cmos level, loss of signal (sfp) or a lvpecl signal detect (sff). 12.2.16.1 100base-fx far end fault indication since auto-negotiation is not specifi ed for 100base-fx, its remote fault capabi lity is unavailabl e. instead, 100base- fx provides an optional far-end fault function. when no signal is being received, the far-end fault feature transmits a specia l far-end fault indication to its far-end peer. the far-end fault indication is sent only when a physical error condition is sensed on the receive channel. the far-end fault i ndication is comprised of three or more repeating cycles, ea ch of 84 ones followed by a single zero. this signal is sent in-band and is readily detectable but is constructed so as to not satisfy the 100base-x carrier sense criterion. far-end fault is implemented through the far-end fault g enerate, far-end fault detect, and the link monitor pro- cesses. the far-end fault generate process is responsible for sensing a receive channel failure (signal_status=off) and transmitting the far-end fault indication in response. the transmission of the far-end fault indication may start or stop at any time depending only on signal_status. the far- end fault detect process continuously monitors the rx pro- cess for the far-end fault indication. dete ction of the far-end fault indication di sables the station by causing the link monitor process to de-assert link_status, which in turn causes the station to source idles. far-end fault is enabled by default while in 100base-fx mode via the far end fault indicati on enable (fefi_en) of the phy special control/status indication register (phy_speci al_control_stat_ind) . 12.2.16.2 100base-fx enable and los/sd selection 100base-fx operation is enabled by the use of the fx mode strap ( fx_mode_strap_1 ) and is reflected in the 100base- fx mode (fx_mode) bit in the phy special modes register (phy_special_modes) . loss of signal mode is selected by the fxlosen strap input pin. figure 12-7: connection loopback block diagram 10/100 ethernet mac xfmr digital rxd txd analog rx tx 12 3 4 5 6 7 8 rj45 loopback cable. created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6. downloaded from: http:///
lan9250 ds00001913a-page 230 ? 2015 microchip technology inc. if loss of signal mode is not selected, th en signal detect mode is selected by the fxsdena strap input pin. when greater than 1 v (typ.), signal detect mode is enabled, wh en less than 1 v (typ.), copper twisted pair is enabled. table 12-8 summarizes the selection. 12.2.17 required ethernet magn etics (100base-tx and 10base-t) the magnetics selected for use with the device should be an auto-mdix style magnetic, which is widely available from several vendors. please review the smsc/microchip appl ication note 8.13 suggested magnetics for the latest quali- fied and suggested magnetics. a list of vendors and pa rt numbers are provided wi thin the application note. 12.2.18 phy registers the phy registers are indirectly accessed through the host mac mii access re gister (hmac_mii_acc) and host mac mii data register (hmac_mii_data) . a list of the mii serial accessible control and status regist ers and their corresponding register index numbers is included in table 12-9 . each individual phy is assigned a unique phy address as detailed in section 12.1.1, "phy addressing," on page 210 . in addition to the mii serial accessible control and status re gisters, a set of indirectly ac cessible registers provides sup- port for the ieee 802.3 section 45.2 mdio manageable device (mmd) registers . a list of these registers and their cor- responding register index numbers is included in table 12-15 . note: the digital reset (digital_rst) bit will cause the eeprom loader to reload the config uration strap val- ues into the phy registers and to reset all other phy regi sters to their default values. an eeprom reload command via the eeprom command register (e2p_cmd) also has the same effect. control and status registers table 12-9 provides a list of supported registers. register details , including bit definitions, are provided in the following subsections. unless otherwise specified, reserved fields must be written with zeros if the register is written. note: the fxsdena strap input pin is shared with the fxsda pin. as such, the lvpecl levels ensure that the input is greater than 1 v (typ.) and that signal dete ct mode is selected. when tp copper is desired, the signal detect input function is not re quired and the pin should be set to 0 v. care must be taken such that an non-powered or di sabled transceiver does not load the signal detect input below the valid lvpecl level. table 12-8: 100base-fx los, sd and tp copper selection fxlosen fxsdena phy mode <1 v (typ.) <1 v (typ.) tp copper >1 v (typ.) 100base-fx signal detect >1 v (typ.) n/a 100base-fx los table 12-9: phy mii serially accessible control and status registers index register name (symbol) group 0 phy basic control regist er (phy_basic_control) basic 1 phy basic status register (phy_basic_status) basic 2 phy identification msb register (phy_id_msb) extended 3 phy identification lsb register (phy_id_lsb) extended 4 phy auto-negotiation advertisement register (phy_an_adv) extended downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 231 lan9250 5 phy auto-negotiation link partner base page ability register (phy_an_lp_base_abil- ity) extended 6 phy auto-negotiation expansion register (phy_an_exp) extended 7 phy auto negotiation next page tx register (phy_an_np_tx) extended 8 phy auto negotiation next page rx register (phy_an_np_rx) extended 13 phy mmd access control register (phy_mmd_access) extended 14 phy mmd access address/data register (phy_mmd_addr_data) extended 16 phyedpd nlp / crossover time / eee c onfiguration regist er (phy_edpd_cfg) vendor- specific 17 phy mode control/status register (phy_mode_control_status) vendor- specific 18 phy special modes register (phy_special_modes) vendor- specific 24 phy tdr patterns/delay control register (phy_tdr_pat_delay) vendor- specific 25 phy tdr control/status register (phy_tdr_control_stat) vendor- specific 26 phy symbol error counter register vendor- specific 27 phy special control/status indication register (p hy_special_control_stat_ind) vendor- specific 28 phy cable length register (phy_cable_len) vendor- specific 29 phy interrupt source flags register (phy_interrupt_source) vendor- specific 30 phy interrupt mask regist er (phy_interrupt_mask) vendor- specific 31 phy special control/status regi ster (phy_special_control_status) vendor- specific table 12-9: phy mii serially accessible control and status registers index register name (symbol) group downloaded from: http:///
lan9250 ds00001913a-page 232 ? 2015 microchip technology inc. 12.2.18.1 phy basic control register (phy_basic_control) this read/write register is used to configure the phy. index (decimal): 0 size: 16 bits bits description type default 15 soft reset (phy_srst) when set, this bit resets all the phy r egisters to their default state, except those marked as nasr type. this bit is self clearing. 0: normal operation 1: reset r/w sc 0b 14 loopback (phy_loopback) this bit enables/disables the loopback mode. when enabled, transmissions are not sent to network. instead, they are looped back into the phy. 0: loopback mode disabled (normal operation) 1: loopback mode enabled r/w 0b 13 speed select lsb (phy_speed_sel_lsb) this bit is used to set the speed of the phy when the auto-negotiation enable (phy_an) bit is disabled. 0: 10 mbps 1: 100 mbps r/w note 4 12 auto-negotiation enable (phy_an) this bit enables/disables auto-n egotiation. when enabled, the speed select lsb (phy_speed_sel_lsb) and duplex mode (phy_duplex) bits are overridden. this bit is forced to a 0 if the 100base-fx mode (fx_mode) bit of the phy special modes register (phy_special_modes) is a high. 0: auto-negotiation disabled 1: auto-negotiation enabled r/w note 5 11 power down (phy_pwr_dwn) this bit controls the power down mode of the phy. 0: normal operation 1: general power down mode r/w 0b 10 reserved ro - 9 restart auto-negotia tion (phy_rst_an) when set, this bit restarts the auto-negotiation process. 0: normal operation 1: auto-negotiation restarted r/w sc 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 233 lan9250 note 4: the default value of this bit is determined by the logical or of the auto-negotiation strap ( autoneg_strap_1 ) and the speed select strap ( speed_strap_1 ). essentially, if the auto-negotiation strap is set, the default value is 1, otherwise the default is determined by the value of the speed select strap. refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx m ode, the default va lue of this bit is a 1. note 5: the default is the value of t he auto-negotiation strap ( autoneg_strap_1 ). refer to section 7.0, "configura- tion straps," on page 54 for more information. in 100base-fx mode, the default value of this bit is a 0. note 6: the default value of this bit is determined by the logi cal and of the negation of the auto-negotiation strap ( autoneg_strap_1 ) and the duplex select strap ( duplex_strap_1 ). essentially, if the auto-negotiation strap is set, the default value is 0, other wise the default is determined by the val ue of the duplex select strap. refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx mode, the auto-negotiati on strap is not considered and the default of this bit is the value of the duplex select strap. 8 duplex mode (phy_duplex) this bit is used to set the duplex when the auto-negotiation enable (phy_an) bit is disabled. 0: half duplex 1: full duplex r/w note 6 7 collision test mode (phy_col_test) this bit enables/disables the collision test mode of the phy. when set, the collision signal is active during transmission. it is recommended that this fea- ture be used only in loopback mode. 0: collision test mode disabled 1: collision test mode enabled r/w 0b 6:0 reserved ro - bits description type default downloaded from: http:///
lan9250 ds00001913a-page 234 ? 2015 microchip technology inc. 12.2.18.2 phy basic status register (phy_basic_status) this register is used to monitor the status of the phy. index (decimal): 1 size: 16 bits bits description type default 15 100base-t4 this bit displays the status of 100base-t4 compatibility. 0: phy not able to perform 100base-t4 1: phy able to perform 100base-t4 ro 0b 14 100base-x full duplex this bit displays the status of 100base-x full duplex compatibility. 0: phy not able to perf orm 100base-x full duplex 1: phy able to perfor m 100base-x full duplex ro 1b 13 100base-x half duplex this bit displays the status of 100base-x half duplex compatibility. 0: phy not able to perform 100base-x half duplex 1: phy able to perform 100base-x half duplex ro 1b 12 10base-t full duplex this bit displays the status of 10base-t full duplex compatibility. 0: phy not able to perform 10base-t full duplex 1: phy able to perfor m 10base-t full duplex ro 1b 11 10base-t half duplex (typ.) this bit displays the status of 10base-t half duplex compatibility. 0: phy not able to perform 10base-t half duplex 1: phy able to perform 10base-t half duplex ro 1b 10 100base-t2 full duplex this bit displays the status of 100base-t2 full duplex compatibility. 0: phy not able to perform 100base-t2 full duplex 1: phy able to perform 100base-t2 full duplex ro 0b 9 100base-t2 half duplex this bit displays the status of 100base-t2 half duplex compatibility. 0: phy not able to perform 100base-t2 half duplex 1: phy able to perform 100base-t2 half duplex ro 0b 8 extended status this bit displays whether extended status information is in register 15 (per ieee 802.3 clause 22.2.4). 0: no extended status information in register 15 1: extended status information in register 15 ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 235 lan9250 7 unidirectional ability this bit indicates whether the phy is able to transmit regardless of whether the phy has determined that a valid link has been established. 0: can only transmit when a valid link has been established 1: can transmit regardless ro 0b 6 mf preamble suppression this bit indicates whether the phy accepts management frames with the pre- amble suppressed. 0: management frames with preamble suppressed not accepted 1: management frames with preamble suppressed accepted ro 0b 5 auto-negotiation complete this bit indicates the status of the auto-negotiation process. 0: auto-negotiation process not completed 1: auto-negotiation process completed ro 0b 4 remote fault this bit indicates if a remote fault condition has been detected. 0: no remote fault condition detected 1: remote fault condition detected ro/lh 0b 3 auto-negotiation ability this bit indicates the phys auto-negotiation ability. 0: phy is unable to perform auto-negotiation 1: phy is able to pe rform auto-negotiation ro 1b 2 link status this bit indicates the status of the link. 0: link is down 1: link is up ro/ll 0b 1 jabber detect this bit indicates the status of the jabber condition. 0: no jabber condition detected 1: jabber condition detected ro/lh 0b 0 extended capability this bit indicates whether extended register capability is supported. 0: basic register set capabilities only 1: extended register set capabilities ro 1b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 236 ? 2015 microchip technology inc. 12.2.18.3 phy identification msb register (phy_id_msb) this read/write register contains the m sb of the organizationally unique identifier (oui) for the phy. the lsb of the phy oui is cont ained in the phy identification lsb register (phy_id_lsb) . index (decimal): 2 size: 16 bits bits description type default 15:0 phy id this field is assigned to the 3rd through 18th bits of the oui, respectively (oui = 00800fh). r/w 0007h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 237 lan9250 12.2.18.4 phy identification lsb register (phy_id_lsb) this read/write register contains the lsb of the organizationally unique identifi er (oui) for the phy. the msb of the phy oui is cont ained in the phy identification msb register (phy_id_msb) . index (decimal): 3 size: 16 bits bits description type default 15:10 phy id this field is assigned to the 19th through 24th bits of the phy oui, respec- tively. (oui = 00800fh). r/w c140h 9:4 model number this field contains the 6-bit manufacturers model number of the phy. r/w 3:0 revision number this field contain the 4-bit manufacturers revision number of the phy. r/w note: the default value of the revision number field may vary dependent on the silicon revision number. downloaded from: http:///
lan9250 ds00001913a-page 238 ? 2015 microchip technology inc. 12.2.18.5 phy auto-negotiation ad vertisement register (phy_an_adv) this read/write register contains the advertised ability of the phy and is used in the auto-negotiation process with the link partner. index (decimal): 4 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 remote fault this bit determines if remote fault indication will be advertised to the link part- ner. 0: remote fault indication not advertised 1: remote fault indication advertised r/w 0b 12 extended next pagenote: this bit should be written as 0. r/w 0b 11 asymmetric pause this bit determines the advertised asymmetric pause capability. 0: no asymmetric pause toward link partner advertised 1: asymmetric pause toward link partner advertised r/w note 7 10 symmetric pause this bit determines the advertised symmetric pause capability. 0: no symmetric pause toward link partner advertised 1: symmetric pause toward link partner advertised r/w note 7 9 reserved ro - 8 100base-x full duplex this bit determines the advertised 100base-x full d uplex capability. 0: 100base-x full duplex ability not advertised 1: 100base-x full duplex ability advertised r/w 1b 7 100base-x half duplex this bit determines the advertised 100base-x half duplex capability. 0: 100base-x half duplex ability not advertised 1: 100base-x half duplex ability advertised r/w 1b 6 10base-t full duplex this bit determines the advertised 10base-t full duplex capability. 0: 10base-t full duplex ability not advertised 1: 10base-t full duplex ability advertised r/w note 8 table 12-10 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 239 lan9250 note 7: the default values of the a symmetric pause and symmetric pause bits are determined by the manual flow control enable strap ( manual_fc_strap_1 ). when the manual flow control enable strap is 0, the symmet- ric pause bit defaults to 1 and the asymmetric pause bit defaults to the setting of the full-duplex flow con- trol enable strap ( fd_fc_strap_1 ). when the manual flow control enable strap is 1, both bits default to 0. refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx mode, the default value of these bits is 0. note 8: the default value of this bit is determined by th e logical or of the auto-negotiation enable strap ( autoneg_strap_1 ) with the logical and of the negated speed select strap ( speed_strap_1 ) and the duplex select strap ( duplex_strap_1 ). table 12-10 defines the default behavior of this bit. refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx m ode, the default va lue of this bit is a 0. note 9: the default value of this bit is determined by the logical or of the auto-negotiation strap ( autoneg_strap_1 ) and the negated speed select strap ( speed_strap_1 ). table 12-11 defines the default behavior of this bit. refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx mode, the default value of this bit is a 0. 5 10base-t half duplex this bit determines the advertise d 10base-t half duple x capability. 0: 10base-t half duplex ability not advertised 1: 10base-t half duplex ability advertised r/w note 9 table 12-11 4:0 selector field this field identifies the type of message being sent by auto-negotiation. 00001: ieee 802.3 r/w 00001b table 12-10: 10base-t full duplex advertisement default value autoneg_strap_1 speed_strap_1 duplex_strap_1 default 10base-t full duplex (bit 6) value 000 0 001 1 010 0 011 0 1xx 1 table 12-11: 10base-t half duplex advertisement bit default value autoneg_strap_1 speed_strap_1 default 10base-t half duplex (bit 5) value 00 1 01 0 10 1 11 1 bits description type default downloaded from: http:///
lan9250 ds00001913a-page 240 ? 2015 microchip technology inc. 12.2.18.6 phy auto-negotia tion link partner base page ability register (phy_an_lp_base_ability) this read-only register contai ns the advertised ability of the link partners phy and is used in the auto-negotiation pro- cess between the link partner and the phy. index (decimal): 5 size: 16 bits bits description type default 15 next page this bit indicates the link partner phy page capability. 0: link partner phy does not ad vertise next page capability 1: link partner phy advertises next page capability ro 0b 14 acknowledge this bit indicates whether the link code word has been received from the partner. 0: link code word not yet received from partner 1: link code word received from partner ro 0b 13 remote fault this bit indicates whether a remote fault has been detected. 0: no remote fault 1: remote fault detected ro 0b 12 extended next page 0: link partner phy does not advertise extended next page capability 1: link partner phy advertises extended next page capability ro 0b 11 asymmetric pause this bit indicates the link partner phy asymmetric pause capability. 0: no asymmetric pause toward link partner 1: asymmetric pause toward link partner ro 0b 10 pause this bit indicates the link partner phy symmetric pause capability. 0: no symmetric pause toward link partner 1: symmetric pause toward link partner ro 0b 9 100base-t4 this bit indicates t he link partner phy 100base-t4 capability. 0: 100base-t4 ability not supported 1: 100base-t4 ability supported ro 0b 8 100base-x full duplex this bit indicates the link partner phy 100base- x full duplex capability. 0: 100base-x full duplex ability not supported 1: 100base-x full duplex ability supported ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 241 lan9250 7 100base-x half duplex this bit indicates the link partner phy 100base- x half duplex capability. 0: 100base-x half duplex ability not supported 1: 100base-x half duplex ability supported ro 0b 6 10base-t full duplex this bit indicates the link partner phy 10base-t full duplex capability. 0: 10base-t full duplex ability not supported 1: 10base-t full duplex ability supported ro 0b 5 10base-t half duplex this bit indicates the link partner phy 10base-t half duplex capability. 0: 10base-t half duplex ability not supported 1: 10base-t half duplex ability supported ro 0b 4:0 selector field this field identifies the type of message being sent by auto-negotiation. 00001: ieee 802.3 ro 00001b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 242 ? 2015 microchip technology inc. 12.2.18.7 phy auto-negotiation expansion register (phy_an_exp) this read/write register is used in the auto-negotiation process between the link partner and the phy. index (decimal): 6 size: 16 bits bits description type default 15:7 reserved ro - 6 receive next page location able 0 = received next page storage location is not specified by bit 6.5 1 = received next page storage lo cation is specified by bit 6.5 ro 1b 5 received next page storage location 0 = link partner next pages are stored in the phy auto-negotiation link partner base page ability regi ster (phy_an_lp_base_ability) (phy register 5) 1 = link partner next pages are stored in the phy auto negotiation next page rx register (phy_an_np_rx) (phy register 8) ro 1b 4 parallel detection fault this bit indicates whether a parallel detection fault has been detected. 0: a fault hasnt been detected via the parallel detection function 1: a fault has been detected vi a the parallel de tection function ro/lh 0b 3 link partner next page able this bit indicates whether the link partner has next page ability. 0: link partner does not contain next page capability 1: link partner contains next page capability ro 0b 2 next page able this bit indicates whether the local device has next page ability. 0: local device does not contain next page capability 1: local device contains next page capability ro 1b 1 page received this bit indicates the reception of a new page. 0: a new page has not been received 1: a new page has been received ro/lh 0b 0 link partner auto -negotiation able this bit indicates the auto-negotiation ability of the link partner. 0: link partner is not auto-negotiation able 1: link partner is auto-negotiation able ro 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 243 lan9250 12.2.18.8 phy auto negotiation next page tx register (phy_an_np_tx) index (in decimal): 7 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable r/w 0b 14 reserved ro - 13 message page 0 = unformatted page 1 = message page r/w 1b 12 acknowledge 2 0 = device cannot co mply with message. 1 = device will comply with message. r/w 0b 11 toggle 0 = previous value was high. 1 = previous value was low. ro 0b 10:0 message code message/unformatted code field r/w 000 0000 0001b downloaded from: http:///
lan9250 ds00001913a-page 244 ? 2015 microchip technology inc. 12.2.18.9 phy auto negotiation next page rx register (phy_an_np_rx) index (in decimal): 8 size: 16 bits bits description type default 15 next page 0 = no next page ability 1 = next page capable ro 0b 14 acknowledge 0 = link code word not yet received from partner 1 = link code word received from partner ro 0b 13 message page 0 = unformatted page 1 = message page ro 0b 12 acknowledge 2 0 = device cannot comply with message. 1 = device will comply with message. ro 0b 11 toggle 0 = previous value was high. 1 = previous value was low. ro 0b 10:0 message code message/unformatted code field ro 000 0000 0000b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 245 lan9250 12.2.18.10 phy mmd access control register (phy_mmd_access) this register in conjunction with the phy mmd access address/data register (phy_mmd_addr_data) provides indirect access to the mdio manageable device (mmd) registers. refer to the mdio manageable device (mmd) reg- isters on page 263 for additional details. index (in decimal): 13 size: 16 bits bits description type default 15:14 mmd function this field is used to select the desired mmd function: 00 = address 01 = data, no post increment 10 = reserved 11 = reserved r/w 00b 13:5 reserved ro - 4:0 mmd device address (devad) this field is used to select the desired mmd device address. (3 = pcs, 7 = auto-negotiation) r/w 0h downloaded from: http:///
lan9250 ds00001913a-page 246 ? 2015 microchip technology inc. 12.2.18.11 phy mmd access address/ data register (phy_mmd_addr_data) this register in conjunction with the phy mmd access control r egister (phy_mmd_access) provides indirect access to the mdio manageable device (mmd) registers. refer to the mdio manageable device (mmd) registers on page 263 for additional details. index (in decimal): 14 size: 16 bits bits description type default 15:0 mmd register address/data if the mmd function field of the phy mmd access control register (phy_mmd_access) is 00, this field is used to indicate the mmd register address to read/write of the device specified in the mmd device address (devad) field. otherwise, this register is used to read/write data from/to the previously specified mmd address. r/w 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 247 lan9250 12.2.18.12 phyedpd nlp / cro ssover time / eee configuratio n register (phy_edpd_cfg) this register is used to enable eee functionality and control nl p pulse generation and the auto-mdix crossover time of the phy. index (decimal): 16 size: 16 bits bits description type default 15 edpd tx nlp enable enables the generation of a normal link pulse (nlp) with a selectable inter- val while in energy detect power-down. 0=disabled, 1=enabled. the energy detect power-down (edpwrdown) bit in the phy mode con- trol/status register (phy_mode_control_status) needs to be set in order to enter energy detect power-down mode and the phy needs to be in the energy detect power-down state in order for this bit to generate the nlp. bit 3 of this register also needs to be set when setting this bit. r/w nasr note 10 0b 14:13 edpd tx nlp inte rval timer select specifies how often a nlp is transmitted while in the energy detect power- down state. 00b: 1 s 01b: 768 ms 10b: 512 ms 11b: 256 ms r/w nasr note 10 00b 12 edpd rx single nlp wake enable when set, the phy will wake upon the reception of a single normal link pulse. when clear, the phy requires two link pluses, within the interval spec- ified below, in order to wake up. single nlp wake mode is recommended when connecting to green net- work devices. r/w nasr note 10 0b 11:10 edpd rx nlp max interval detect select these bits specify the maximum time between two consecutive normal link pulses in order for them to be considered a valid wake up signal. 00b: 64 ms 01b: 256 ms 10b: 512 ms 11b: 1 s r/w nasr note 10 00b 9:3 reserved ro - 2 phy energy efficient et hernet enable (phyeeeen) when set, enables energy efficient et hernet (eee) operation in the phy. when cleared, eee operation is disabled. refer to section 12.2.11, "energy efficient ethernet," on page 223 for addi- tional information. r/w nasr note 10 note 11 downloaded from: http:///
lan9250 ds00001913a-page 248 ? 2015 microchip technology inc. note 10: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy basic control regist er (phy_basic_control) is set. note 11: the default value of this bit is a 0 if in 100base-fx mode, otherwise the default value of this bit is deter- mined by the energy efficient ethernet enable strap ( eee_enable_strap_1 ). refer to section 7.0, "config- uration straps," on page 54 for more information. 1 edpd extend crossover when in energy detect power-down (edpd) mode ( energy detect power- down (edpwrdown) = 1), setting this bit to 1 extends the crossover time by 2976 ms. 0 = crossover time extension disabled 1 = crossover time extension enabled (2976 ms) r/w nasr note 10 0b 0 extend manual 10/100 auto-mdix crossover time when auto-negotiation is disabled, setting this bit extends the auto-mdix crossover time by 32 sample times (32 * 62 ms = 1984 ms). this allows the link to be established with a partner phy that has auto-negotiation enabled. when auto-negotiation is enabled, this bit has no affect. it is recommended that this bit is set when disabling an with auto-mdix enabled. r/w nasr note 10 1b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 249 lan9250 12.2.18.13 phy mode control/status register (phy_mode_control_status) this read/write register is us ed to control and monitor various phy configuration options. note 12: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy basic control regist er (phy_basic_control) is set. index (decimal): 17 size: 16 bits bits description type default 15:14 reserved ro - 13 energy detect power-down (edpwrdown) this bit controls the energy detect power-down mode. 0: energy detect power-down is disabled 1: energy detect power-down is enabled note: when in edpd mode, the devices nlp characteristics can be modified via the phyedpd nlp / crossover time / eee configuration register (phy_edpd_cfg) . r/w 0b 12:7 reserved ro - 6 altint alternate interrupt mode: 0 = primary interrupt system enabled (default) 1 = alternate interrupt system enabled refer to section 12.2.9, "phy interrupts," on page 220 for additional informa- tion. r/w nasr note 12 0b 5:2 reserved ro - 1 energy on (energyon) indicates whether energy is detected. this bit transitions to 0 if no valid energy is detected within 256 ms (1500 ms if auto-negotiation is enabled). it is reset to 1 by a hardware reset and by a software reset if auto-negotiation was enabled or will be enabled via strapping. refer to section 12.2.10.2, "energy detect power-down," on page 223 for additional information. ro 1b 0 reserved ro - downloaded from: http:///
lan9250 ds00001913a-page 250 ? 2015 microchip technology inc. 12.2.18.14 phy special modes register (phy_special_modes) this read/write register is used to control the special modes of the phy. note 13: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy basic control regist er (phy_basic_control) is set. note 14: the default value of this bit is determined by the fiber enable strap ( fx_mode_strap_1 ). note 15: the default value of this field is determined by a co mbination of the configuration straps autoneg_strap_1, speed_strap_1, and duplex_strap_1. if the autoneg_strap_1 is 1, then the default mo de[2:0] value is 111b. else, the default value of this field is de termined by the remain ing straps. mode[2]=0, mode[1]=( speed_strap_1 ), and mode[0]=( duplex_strap_1 ). refer to section 7.0, "configuration straps," on page 54 for more information. in 100base-fx mode, th e default value of these bits is 010b or 011b. depending on the duplex configuration strap. note 16: the default value of this field is determined per section 12.1.1, "phy addressing," on page 210 . index (decimal): 18 size: 16 bits bits description type default 15:11 reserved ro - 10 100base-fx mode (fx_mode) this bit enables 100base-fx mode note: fx_mode cannot properly be changed with this bit. this bit must always be written with its current va lue. device strapping must be used to set the desired mode. r/w nasr note 13 note 14 9:8 reserved ro - 7:5 phy mode (mode[2:0]) this field controls the phy mode of operation. refer to table 12-12 for a defi- nition of each mode. note: this field should be written with its read value. r/w nasr note 13 note 15 4:0 phy address (phyadd) the phy address field determines the mmi address to which the phy will respond and is also used for initialization of the cipher (scrambler) key. refer to section 12.1.1, "phy addressing," on page 210 for additional information. r/w nasr note 13 note 16 table 12-12: mode[2:0] definitions mode[2:0] mode definitions 000 10base-t half duplex. au to-negotiation disabled. 001 10base-t full duplex. au to-negotiation disabled. 010 100base-tx or 100base-fx half duplex. au to-negotiation disabled. crs is active during transmit & receive. 011 100base-tx or 100base-fx full duplex. auto-negotiation disabled. crs is active during receive. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 251 lan9250 100 100base-tx full duplex is advertised. auto-negotiation enabled. crs is active during receive. 101 reserved 110 power down mode. 111 all capable. auto-negotiation enabled. table 12-12: mode[2:0] definitions (continued) mode[2:0] mode definitions downloaded from: http:///
lan9250 ds00001913a-page 252 ? 2015 microchip technology inc. 12.2.18.15 phy tdr patterns/delay control register (phy_tdr_pat_delay) note 17: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy basic control regist er (phy_basic_control) is set. index (in decimal): 24 size: 16 bits bits description type default 15 tdr delay in 0 = line break time is 2 ms. 1 = the device uses tdr line break counter to increase the line break time before starting tdr. r/w nasr note 17 1b 14:12 tdr line break counter when tdr delay in is 1, this field specifies the increase in line break time in increments of 256 ms, up to 2 seconds. r/w nasr note 17 001b 11:6 tdr pattern high this field specifies the data patter n sent in tdr mode for the high cycle. r/w nasr note 17 101110b 5:0 tdr pattern low this field specifies the data pattern sent in tdr mode for the low cycle. r/w nasr note 17 011101b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 253 lan9250 12.2.18.16 phy tdr control/status register (phy_tdr_control_stat) note 18: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy basic control regist er (phy_basic_control) is set. index (in decimal): 25 size: 16 bits bits description type default 15 tdr enable 0 = tdr mode disabled 1 = tdr mode enabled note: this bit self clears when tdr completes ( tdr channel status goes high) r/w nasr sc note 18 0b 14 tdr analog to digital filter enable 0 = tdr analog to digital filter disabled 1 = tdr analog to digital filter enabled (reduces noise spikes during tdr pulses) r/w nasr note 18 0b 13:11 reserved ro - 10:9 tdr channel cable type indicates the cable type det ermined by the tdr test. 00 = default 01 = shorted cable condition 10 = open cable condition 11 = match cable condition r/w nasr note 18 00b 8 tdr channel status when high, this bit indicates that the tdr operation has completed. this bit will stay high until reset or the tdr operation is restarted ( tdr enable = 1) r/w nasr note 18 0b 7:0 tdr channel length this eight bit value indicates the tdr channel length during a short or open cable condition. refer to section 12.2.14.1, "time domain reflectometry (tdr) cable diagnostics," on page 225 for additional information on the usage of this field. note: this field is not valid during a match cable condition. the phy cable length register (phy_cable_len) must be used to determine cable length during a non-open/short (match) condition. refer to section 12.2.14, "cable diagnostics," on page 224 for additional information. r/w nasr note 18 00h downloaded from: http:///
lan9250 ds00001913a-page 254 ? 2015 microchip technology inc. 12.2.18.17 phy symbol error counter register index (in decimal): 26 size: 16 bits bits description type default 15:0 symbol error coun ter (sym_err_cnt) this 100base-tx receiver-based error counter increments when an invalid code symbol is received, including idle symbols. the counter is incre- mented only once per packet, even when the received packet contains more than one symbol error. this field counts up to 65,536 and rolls over to 0 if incremented beyond its maximum value. note: this register is cleared on reset, but is not cleared by reading the register. it does not increment in 10base-t mode. ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 255 lan9250 12.2.18.18 phy special control/status indica tion register (phy_spec ial_control_stat_ind) this read/write register is used to control various options of the phy. index (decimal): 27 size: 16 bits bits description type default 15 auto-mdix contro l (amdixctrl) this bit is responsible for determining the source of auto-mdix control for the port. when set, the manual md ix and auto mdix straps ( manual_mdix- _strap_1 / auto_mdix_strap_1 ) are overridden, and auto-mdix functions are controlled using the amdixen and amdixs tate bits of this register. when cleared, auto-mdix functi onality is controlled by the manual mdix and auto mdix straps by default. refer to section 7.0, "configur ation straps," on page 54 for configuration strap definitions. 0: port auto-mdix determ ined by strap inputs ( table 12-14 ) 1: port auto-mdix determined by bits 14 and 13 note: the value of auto_mdix_strap_1 is indicated in the amdix_en strap state bit of the hardware configuration register (hw_cfg) . r/w nasr note 19 0b 14 auto-mdix enable (amdixen) when the amdixctrl bit of this register is set, this bit is used in conjunction with the amdixstate bit to control t he port auto-mdix functionality as shown in table 12-13 . auto-mdix is not appropriate and should not be enabled for 100base-fx mode. r/w nasr note 19 0b 13 auto-mdix state (amdixstate) when the amdixctrl bit of this register is set, this bit is used in conjunction with the amdixen bit to cont rol the port auto-mdix functionality as shown in table 12-13 . r/w nasr note 19 0b 12 reserved ro - 11 sqe test disable (sqeoff) this bit controls the disabling of th e sqe test (heartbeat). sqe test is enabled by default. 0: sqe test enabled 1: sqe test disabled r/w nasr note 19 0b 10:6 reserved ro - 5 far end fault indication enable (fefi_en) this bit enables far end fault generation and detection. see section 12.2.16.1, "100base-fx far end f ault indication," on page 229 for more information. r/w note 20 4 10base-t polarity state (xpol) this bit shows the polarity state of the 10base-t. 0: normal polarity 1: reversed polarity ro 0b downloaded from: http:///
lan9250 ds00001913a-page 256 ? 2015 microchip technology inc. note 19: register bits designated as nasr are reset when the phy reset is generated via the reset control reg- ister (reset_ctl) . the nasr designation is only applicable when the soft reset (phy_srst) bit of the phy basic control regist er (phy_basic_control) is set. note 20: the default value of this bit is a 1 if in 100base-fx mode, otherwise the default is a 0. 3:0 reserved ro - table 12-13: auto-mdix enable and auto-mdix state bit functionality auto-mdix enable auto-mdix state mode 0 0 manual mode, no crossover 0 1 manual mode, crossover 1 0 auto-mdix mode 1 1 reserved (do not use this state) table 12-14: mdix strap functionality auto_mdix_strap_1 manual_mdix_strap_1 mode 0 0 manual mode, no crossover 0 1 manual mode, crossover 1 x auto-mdix mode bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 257 lan9250 12.2.18.19 phy cable length register (phy_cable_len) index (in decimal): 28 size: 16 bits bits description type default 15:12 cable length (cbln) this four bit value indicates the cable length. refer to section 12.2.14.2, "matched cable diagnostics," on page 227 for additional information on the usage of this field. note: this field indicates cable leng th for 100base-tx linked devices that do not have an open/short on the cable. to determine the open/short status of the cable, the phy tdr patterns/delay control register (phy_tdr_pat_delay) and phy tdr control/ status register (phy_tdr_control_stat) must be used. cable length is not supported for 10base-t links. refer to section 12.2.14, "cable diagnostics," on page 224 for additional information. ro 0000b 11:0 reserved - write as 100000000000b, ignore on read r/w - downloaded from: http:///
lan9250 ds00001913a-page 258 ? 2015 microchip technology inc. 12.2.18.20 phy interrupt source flags register (phy_interrupt_source) this read-only register is used to determine to source of va rious phy interrupts. all interrupt source bits in this register are read-only and latch high upon detection of the corresponding interrupt (if enabled). a read of this register clears the interrupts. these interrupts are enabled or masked via the phy interrupt mask regist er (phy_interrupt_mask) . index (decimal): 29 size: 16 bits bits description type default 15:9 reserved ro - 9 int9 this interrupt source bit indicates a link up (link status asserted). 0: not source of interrupt 1: link up (link status asserted) ro/lh 0b 8 reserved ro - 7 int7 this interrupt source bit indicates when the energy on (energyon) bit of the phy mode control/status register (phy_mode_control_status) has been set. 0: not source of interrupt 1: energyon generated ro/lh 0b 6 int6 this interrupt source bit indicates auto-negotiation is complete. 0: not source of interrupt 1: auto-negotia tion complete ro/lh 0b 5 int5 this interrupt source bit indicate s a remote fault has been detected. 0: not source of interrupt 1: remote fault detected ro/lh 0b 4 int4 this interrupt source bit indicates a link down (link status negated). 0: not source of interrupt 1: link down (link status negated) ro/lh 0b 3 int3 this interrupt source bit indicates an auto-negotiation lp acknowledge. 0: not source of interrupt 1: auto-negotiation lp acknowledge ro/lh 0b 2 int2 this interrupt source bit indicates a parallel detection fault. 0: not source of interrupt 1: parallel detection fault ro/lh 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 259 lan9250 1 int1 this interrupt source bit indicates an auto-negotiation page received. 0: not source of interrupt 1: auto-negotiation page received ro/lh 0b 0 reserved ro - bits description type default downloaded from: http:///
lan9250 ds00001913a-page 260 ? 2015 microchip technology inc. 12.2.18.21 phy interrupt mask re gister (phy_interrupt_mask) this read/write register is used to enable or mask the various phy interrupts and is used in conjunction with the phy interrupt source flags regi ster (phy_interrupt_source) . index (decimal): 30 size: 16 bits bits description type default 15:10 reserved ro - 9 int9_mask this interrupt mask bit enables/masks the link up (link status asserted) inter- rupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 8 reserved ro - 7 int7_mask this interrupt mask bit enables /masks the energyon interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 6 int6_mask this interrupt mask bi t enables/masks the auto -negotiation interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 5 int5_mask this interrupt mask bi t enables/masks the remo te fault interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 4 int4_mask this interrupt mask bit en ables/masks the link down (link status negated) interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 3 int3_mask this interrupt mask bit enables/masks the auto-negotiation lp acknowledge interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 2 int2_mask this interrupt mask bit en ables/masks the parallel de tection fault interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 261 lan9250 1 int1_mask this interrupt mask bit enables/masks the auto-negotiation page received interrupt. 0: interrupt source is masked 1: interrupt source is enabled r/w 0b 0 reserved ro - bits description type default downloaded from: http:///
lan9250 ds00001913a-page 262 ? 2015 microchip technology inc. 12.2.18.22 phy special control/status register (phy_specia l_control_status) this read/write register is used to control and monitor various options of the phy. index (decimal): 31 size: 16 bits bits description type default 15:13 reserved ro - 12 autodone this bit indicates the status of the auto-negotiation on the phy. 0: auto-negotiation is not complete d, is disabled, or is not active 1: auto-negotiation is completed ro 0b 11:5 reserved - write as 00 00010b, ignore on read r/w 0000010b 4:2 speed indication this field indicates the current phy speed configuration. ro xxxb 1:0 reserved ro 0b state description 000 reserved 001 10base-t half-duplex 010 100base-tx half-duplex 011 reserved 100 reserved 101 10base-t full-duplex 110 100base-tx full-duplex 111 reserved downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 263 lan9250 mdio manageable device (mmd) registers the device mmd registers adhere to the ieee 802.3-2008 45.2 mdio interface registers specification. the mmd reg- isters are not memory mapped. these re gisters are accessed indirectly via the phy mmd access control register (phy_mmd_access) and phy mmd access address/data register (phy_mmd_addr_data) . the supported mmd device addresses are 3 (pcs), 7 (auto-ne gotiation), and 30 (vendor specific). table 12-15, "mmd registers" details the supported registers within each mmd device. to read or write an mmd register, the following procedure must be observed: 1. write the phy mmd access control re gister (phy_mmd_access) with 00b (address) for the mmd function field and the desired mmd device (3 for pcs, 7 for auto-negotiation) for the mmd device address (devad) field. 2. write the phy mmd access address/data register (phy_mmd_addr_data) with the 16-bit address of the desired mmd register to read/write within the previous ly selected mmd device (pcs or auto-negotiation). table 12-15: mmd registers mmd device address (in decimal) index (in decimal) register name 3 (pcs) 0 phy pcs control 1 register (phy_pcs_ctl1) 1 phy pcs status 1 register (phy_pcs_stat1) 5 phy pcs mmd devices present 1 register (phy_pcs_mmd_present1) 6 phy pcs mmd devices present 2 register (phy_pcs_mmd_present2) 20 phy eee capability register (phy_eee_cap) 22 phy eee wake error register (phy_eee_wake_err) 7 (auto-negotiation) 5 phy auto-negotiation mmd devices present 1 register (phy_an_m- md_present1) 6 phy auto-negotiation mmd devices present 2 register (phy_an_m- md_present2) 60 phy eee advertisement r egister (phy_eee_adv) 61 phy eee link partner advertisem ent register (phy_eee_lp_adv) 30 (vendor specific) 2 phy vendor specific mmd 1 device id 1 register (phy_vend_spec_mmd1_devid1) 3 phy vendor specific mmd 1 device id 2 register (phy_vend_spec_mmd1_devid2) 5 phy vendor specific mmd 1 devices present 1 register (phy_vend_spec_mmd1_present1) 6 phy vendor specific mmd 1 devices present 2 register (phy_vend_spec_mmd1_present2) 8 phy vendor specific mmd 1 status register (phy_vend_spec_m- md1_stat) 14 phy vendor specific mmd 1 package id 1 register (phy_vend_spec_mmd1_pkg_id1) 15 phy vendor specific mmd 1 package id 2 register (phy_vend_spec_mmd1_pkg_id2) downloaded from: http:///
lan9250 ds00001913a-page 264 ? 2015 microchip technology inc. 3. write the phy mmd access control register (phy_mmd_access) with 01b (data) for the mmd function field and choose the previously selected mmd device (3 for pcs, 7 for auto-negotiation) for the mmd device address (devad) field. 4. if reading, read the phy mmd access address/data register (phy_mmd_addr_data) , which contains the selected mmd register conten ts. if writing, write the phy mmd access address/data register (phy_mmd_ad- dr_data) with the register contents intended for the previously selected mmd register. unless otherwise specified, reserved fields must be written with zeros if the register is written. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 265 lan9250 12.2.18.23 phy pcs control 1 register (phy_pcs_ctl1) index (in decimal): 3.0 size: 16 bits bits description type default 15:11 reserved ro - 10 clock stop enable 0 = the phy cannot stop the clock during low power idle (lpi) 1 = the phy may stop the clock during lpi note: this bit has no affect since the device does not support this mode. r/w 0b 9:0 reserved ro - downloaded from: http:///
lan9250 ds00001913a-page 266 ? 2015 microchip technology inc. 12.2.18.24 phy pcs status 1 register (phy_pcs_stat1) index (in decimal): 3.1 size: 16 bits bits description type default 15:12 reserved ro - 11 tx lpi received 0 = tx pcs has not received lpi 1 = tx pcs has received lpi ro/lh 0b 10 rx lpi received 0 = rx pcs has not received lpi 1 = rx pcs has received lpi ro/lh 0b 9 tx lpi indication 0 = tx pcs is not currently receiving lpi 1 = tx pcs is currently receiving lpi ro 0b 8 rx lpi indication 0 = rx pcs is not currently receiving lpi 1 = rx pcs is currently receiving lpi ro 0b 7 reserved ro - 6 clock stop capable 0 = the mac cannot stop the clock during low power idle (lpi) 1 = the mac may stop the clock during lpi note: the device does not support this mode. ro 0b 5:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 267 lan9250 12.2.18.25 phy pcs mmd devices presen t 1 register (phy_pcs_mmd_present1) index (in decimal): 3.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b downloaded from: http:///
lan9250 ds00001913a-page 268 ? 2015 microchip technology inc. 12.2.18.26 phy pcs mmd devices presen t 2 register (phy_pcs_mmd_present2) index (in decimal): 3.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 269 lan9250 12.2.18.27 phy eee capability register (phy_eee_cap) note 21: the default value of this field is determined by the value of the phy energy efficient et hernet enable (phy- eeeen) of the phyedpd nlp / crossover time / eee configur ation register (phy_edpd_cfg) on page 247 . if phy energy efficient ethernet enable (phyeeeen) is 0b, this field is 0b and 100base-tx eee capability is not supported. if phy energy efficient et hernet enable (phyeeeen) is 1b, then this field is 1b and 100base-tx eee capabi lity is supported. index (in decimal): 3.20 size: 16 bits bits description type default 15:7 reserved ro - 6 10gbase-kr eee 0 = eee is not supported for 10gbase-kr 1 = eee is supported for 10gbase-kr note: the device does not support this mode. ro 0b 5 10gbase-kx4 eee 0 = eee is not supported for 10gbase-kx4 1 = eee is supported for 10gbase-kx4 note: the device does not support this mode. ro 0b 4 10gbase-kx eee 0 = eee is not supported for 10gbase-kx 1 = eee is supported for 10gbase-kx note: the device does not support this mode. ro 0b 3 10gbase-t eee 0 = eee is not supported for 10gbase-t 1 = eee is supported for 10gbase-t note: the device does not support this mode. ro 0b 2 1000base-t eee 0 = eee is not supported for 1000base-t 1 = eee is supported for 1000base-t note: the device does not support this mode. ro 0b 1 100base-tx eee 0 = eee is not supported for 100base-tx 1 = eee is supported for 100base-tx ro note 21 0 reserved ro - downloaded from: http:///
lan9250 ds00001913a-page 270 ? 2015 microchip technology inc. 12.2.18.28 phy eee wake error register (phy_eee_wake_err) index (in decimal): 3.22 size: 16 bits bits description type default 15:0 eee wake error counter this counter is cleared to zeros on read and is held to all ones on overflow. ro/rc 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 271 lan9250 12.2.18.29 phy auto-negotiation mmd device s present 1 register (phy_an_mmd_present1) index (in decimal): 7.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b downloaded from: http:///
lan9250 ds00001913a-page 272 ? 2015 microchip technology inc. 12.2.18.30 phy auto-negotiation mmd device s present 2 register (phy_an_mmd_present2) index (in decimal): 7.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 273 lan9250 12.2.18.31 phy eee advertisement register (phy_eee_adv) note 22: this bit is read/write (r/w). however, the user must not set this bit if eee is disabled. note 23: the default value of this field is determined by the value of the phy energy efficient et hernet enable (phy- eeeen) of the phyedpd nlp / crossover time / eee configur ation register (phy_edpd_cfg) on page 247 . if phy energy efficient ethernet enable (phyeeeen) is 0b, this field is 0b and 100base-tx eee capability is not advertised. if phy energy efficient ethernet enable (phyeeeen) is 1b, then this field is 1b and 100base-tx eee capability is advertised. index (in decimal): 7.60 size: 16 bits bits description type default 15:2 reserved ro - 1 100base-tx eee 0 = do not advertise eee capability for 100base-tx. 1 = advertise eee capability for 100base-tx. note 22 note 23 0 reserved ro - downloaded from: http:///
lan9250 ds00001913a-page 274 ? 2015 microchip technology inc. 12.2.18.32 phy eee link partner advert isement register (phy_eee_lp_adv) index (in decimal): 7.61 size: 16 bits bits description type default 15:7 reserved ro - 6 10gbase-kr eee 0 = link partner does not advertise eee capability for 10gbase-kr. 1 = link partner advertises eee capability for 10gbase-kr. note: this device does not support this mode. ro 0b 5 10gbase-kx4 eee 0 = link partner does not advertise eee capability for 10gbase-kx4. 1 = link partner advertises eee capability for 10gbase-kx4. note: this device does not support this mode. ro 0b 4 10gbase-kx eee 0 = link partner does not advertise eee capability for 10gbase-kx. 1 = link partner advertises eee capability for 10gbase-kx. note: this device does not support this mode. ro 0b 3 10gbase-t eee 0 = link partner does not advertise eee capability for 10gbase-t. 1 = link partner advertises eee capability for 10gbase-t. note: this device does not support this mode. ro 0b 2 1000base-t eee 0 = link partner does not advertise eee capability for 1000base-t. 1 = link partner advertises eee capability for 1000base-t. note: this device does not support this mode. ro 0b 1 100base-tx eee 0 = link partner does not advertise eee capability for 100base-tx. 1 = link partner advertises eee capability for 100base-tx. ro 0b 0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 275 lan9250 12.2.18.33 phy vendor specific mmd 1 device id 1 register (phy _vend_spec_mmd1_devid1) index (in decimal): 30.2 size: 16 bits bits description type default 15:0 reserved ro 0000h downloaded from: http:///
lan9250 ds00001913a-page 276 ? 2015 microchip technology inc. 12.2.18.34 phy vendor specific mmd 1 device id 2 register (phy_vend_spec_mmd1_devid2) index (in decimal): 30.3 size: 16 bits bits description type default 15:0 reserved ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 277 lan9250 12.2.18.35 phy vendor specific mmd 1 devices present 1 register (phy_vend_spec_mmd1_present1) index (in decimal): 30.5 size: 16 bits bits description type default 15:8 reserved ro - 7 auto-negotiation present 0 = auto-negotiation not present in package 1 = auto-negotiation present in package ro 1b 6 tc present 0 = tc not present in package 1 = tc present in package ro 0b 5 dte xs present 0 = dte xs not present in package 1 = dte xs present in package ro 0b 4 phy xs present 0 = phy xs not present in package 1 = phy xs present in package ro 0b 3 pcs present 0 = pcs not present in package 1 = pcs present in package ro 1b 2 wis present 0 = wis not present in package 1 = wis present in package ro 0b 1 pmd/pma present 0 = pmd/pma not present in package 1 = pmd/pma present in package ro 0b 0 clause 22 registers present 0 = clause 22 registers not present in package 1 = clause 22 registers present in package ro 0b downloaded from: http:///
lan9250 ds00001913a-page 278 ? 2015 microchip technology inc. 12.2.18.36 phy vendor specific mmd 1 devices present 2 register (phy_vend_spec_mmd1_present2) index (in decimal): 30.6 size: 16 bits bits description type default 15 vendor specific device 2 present 0 = vendor specific device 2 not present in package 1 = vendor specific device 2 present in package ro 0b 14 vendor specific device 1 present 0 = vendor specific device 1 not present in package 1 = vendor specific device 1 present in package ro 1b 13 clause 22 extension present 0 = clause 22 extension not present in package 1 = clause 22 extension present in package ro 0b 12:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 279 lan9250 12.2.18.37 phy vendor specific mmd 1 status register (phy_vend_spec_mmd1_stat) index (in decimal): 30.8 size: 16 bits bits description type default 15:14 device present 00 = no device responding at this address 01 = no device responding at this address 10 = device responding at this address 11 = no device responding at this address ro 10b 13:0 reserved ro - downloaded from: http:///
lan9250 ds00001913a-page 280 ? 2015 microchip technology inc. 12.2.18.38 phy vendor specific mmd 1 packa ge id 1 register (phy_vend_spec_mmd1_pkg_id1) index (in decimal): 30.14 size: 16 bits bits description type default 15:0 reserved ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 281 lan9250 12.2.18.39 phy vendor specific mmd 1 package id 2 register (phy_vend_spec_mmd1_pkg_id2) . index (in decimal): 30.15 size: 16 bits bits description type default 15:0 reserved ro 0000h downloaded from: http:///
lan9250 ds00001913a-page 282 ? 2015 microchip technology inc. 13.0 i 2 c master eeprom controller 13.1 functional overview this chapter details the eeprom i 2 c master and eeprom loader provided by the device. the i 2 c eeprom controller is an i 2 c master module which interfaces an optional extern al eeprom with the system register bus and the eeprom loader. multiple sizes of exte rnal eeproms are supported. co nfiguration of the eeprom si ze is accomplished via the eeprom_size_strap configuration strap. various commands are supported for eeprom access, allowing for the storage and retrieval of static data. the i 2 c interface conforms to the nxp i 2 c-bus specification . the eeprom loader provides th e automatic loading of conf iguration sett ings from the eeprom into the device at reset. the eeprom loader module interfaces to the eepr om controller, ethernet ph ys and the system csrs. 13.2 i 2 c overview i 2 c is a bi-directional 2-wire data protocol. a device that send s data is defined as a transmitte r and a device that receives data is defined as a receiver. the bus is c ontrolled by a master which generates the eescl clock, controls bus access and generates the start and stop conditions. either a master or slave may operate as a transmitter or receiver as deter- mined by the master. both the clock ( eescl ) and data ( eesda ) signals have digital input filters that reject pulses that are less than 100 ns. the data pin is driven low when either interface s ends a low, emulating the wired-and function of the i 2 c bus. the following bus states exist: idle: both eesda and eescl are high when the bus is idle. start & stop conditions: a start condition is defined as a high to low transition on the eesda line while eescl is high. a stop condition is defined as a low to high transition on the eesda line while eescl is high. the bus is considered to be busy following a start condition and is considered free 4.7 s/1.3 s (for 100 khz and 400 khz operation, respectively) following a stop condition. the bus stays busy following a repeated start condition (instead of a stop condition). starts and rep eated starts are otherwise functionally equivalent. data valid: data is valid, following the start condition, when eesda is stable while eescl is high. data can only be changed while the clock is low. there is one valid bit per clock pulse. every byte must be 8 bits long and is transmitted msb first. acknowledge: each byte of data is followed by an acknowled ge bit. the master generates a ninth clock pulse for the acknowledge bit. the transmitter releases eesda (high). the receiver drives eesda low so that it remains valid during the high period of the clock, taking into account the setup and hold times. the receiver may be the master or the slave depending on the direction of the dat a. typically the receiver acknowledges each byte. if the master is the receiver, it does not generate an acknowledge on the last byte of a transf er. this informs the slave to not drive the next byte of data so that the master ma y generate a stop or repeated start condition. figure 13-1 displays the various bus states of a typical i 2 c cycle. figure 13-1: i 2 c cycle eesda eescl s start condition p stop condition data valid or ack data valid or ack data stable data can change data stable data can change sr re-start condition data can change data can change downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 283 lan9250 13.3 i 2 c master eeprom controller the i 2 c eeprom controller supports i 2 c compatible eeproms. note: when the eeprom loader is running, it has exclusive use of the i 2 c eeprom controller. refer to section 13.4, "eeprom loader" for more information. the i 2 c master implements a low level serial interface (start and stop condition generation, data bit transmission and reception, acknowledge generation an d reception) for connection to i 2 c eeproms and consists of a data wire ( eesda ) and a serial clock ( eescl ). the serial clock is driven by the master, while the data wire is bi-directional. both signals are open-drain and require external pull-up resistors. the i 2 c master interface runs at the standard-mode rate of 100 khz. i 2 c master interface timing information is detailed in figure 13-2 and table 13-1 . figure 13-2: i 2 c master timing table 13-1: i 2 c master timing values symbol description min typ max units f scl eescl clock frequency 100 khz t high eescl high time 4.0 ? s t low eescl low time 4.7 ? s t r rise time of eesda and eescl 1000 ns t f fall time of eesda and eescl 300 ns t su;sta setup time (provided to slave) of eescl high before eesda output falling for repeated start con- dition 5.2 note 1 ? s t hd;sta hold time (provided to slave) of eescl after eesda output falling for start or repeated start con- dition 4.5 note 1 ? s t su;dat;in setup time (from slave) eesda input before eescl rising 200 note 2 ns t hd;dat;in hold time (from slave) of eesda input after eescl falling 0n s t su;dat;out setup time (provided to slave) eesda output before eescl rising 1250 note 3 ns eesda (out) eescl s p sr s t f t r t hd;sta t hd;dat;in t su;dat;in t su;sta t su;sto t buf t sp eesda (in) t high t low t hd;dat;out t sp t sp t su;dat;out downloaded from: http:///
lan9250 ds00001913a-page 284 ? 2015 microchip technology inc. note 1: these values provide 500 ns of margin compared to the i 2 c specification. note 2: this value provides 50 ns of margin compared to the i 2 c specification. note 3: these values provide 1000 ns of margin compared to the i 2 c specification. based on the eeprom_size_strap configuration strap, various sized i 2 c eeproms are supported. the varying size ranges are supported by additional bits in the eeprom controller address (epc_address) field of the eeprom command register (e2p_cmd) . within each size range, the largest eeprom uses all the address bits, while the smaller eeproms treat the upper address bits as dont care s. the eeprom controller driv es all the address bits as requested regardless of the actual size of the eeprom. the supported size ranges for i 2 c operation are shown in table 13-2 . note 4: bits in the control byte are used as the upper address bits. 13.3.1 i 2 c eeprom device addressing the i 2 c eeprom is addressed for a read or write operation by first sending a cont rol byte followed by the address byte or bytes. the control byte is preceded by a start condition. the control byte and address byte(s) are each acknowledged by the eeprom slave. if the eeprom slave fails to send an acknowledge, then the sequen ce is aborted (a start con- dition and a stop condition are sent) and the eeprom controller ti meout (epc_timeout) bit of the eeprom com- mand register (e2p_cmd) is set. the control byte consists of a 4 bit cont rol code, 3 bits of chip/block select an d one direction bit. the control code is 1010b. for single byte addressing eeproms, the chip/block se lect bits are used for address bits 10, 9 and 8. for double byte addressing eeproms, the ch ip/block select bits are set lo w. the direction bit is set lo w to indicate the address is being written. t hd;dat;out hold time (provided to slave) of eesda output after eescl falling 1000 note 3 ns t su;sto setup time (provided to slave) of eescl high before eesda output rising for stop condition 4.5 note 1 ? s t buf bus free time 4.7 ? s t sp input spike suppression on eescl and eesda 100 ns table 13-2: i 2 c eeprom size ranges eeprom_size_strap # of address bytes eeprom size eeprom types 01 ( note 4 ) 128 x 8 through 2048 x 8 24xx01, 24xx02, 24xx04, 24xx08, 24xx16 1 2 4096 x 8 through 65536 x 8 24xx32, 24xx64, 24xx128, 24xx256, 24xx512 table 13-1: i 2 c master timing values (continued) symbol description min typ max units downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 285 lan9250 figure 13-3 illustrates a typical i 2 c eeprom addressing bit order for single and double byte addressing. 13.3.2 i 2 c eeprom byte read following the device addressing, a data byte may be read fr om the eeprom by outputting a start condition and control byte with a control code of 1010b, chip/block select bits as described in section 13.3.1 and the r/~w bit high. the eeprom will respond with an acknowledge, followed by 8 bits of data. if the eeprom slave fails to send an acknowl- edge, then the sequence is aborted (a star t condition and a stop condition are sent) and the eeprom controller tim- eout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. the i 2 c master then sends a no- acknowledge, followed by a stop condition. figure 13-4 illustrates a typical i 2 c eeprom byte read for single and double byte addressing. for a register level description of a read operation, refer to section 13.3.7, "i2c master eeprom controller operation," on page 288 . 13.3.3 i 2 c eeprom sequential byte reads following the device addressing, data bytes may be read seque ntially from the eeprom by outputting a start condition and control byte with a control code of 1010 b, chip/block select bits as described in section 13.3.1 and the r/~w bit high. the eeprom will respond with an acknowledge, followed by 8 bits of data. if the eeprom slave fails to send an acknowledge, then the sequence is aborted (a star t condition and a stop condition are sent) and the eeprom controller timeout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. the i 2 c master then sends an acknowledge and the eeprom responds with the next 8 bits of da ta. this continues until the last desired byte is read, at which point the i 2 c master sends a no-acknowledge (instead of t he acknowledge), followed by a stop condition. figure 13-3: i 2 c eeprom addressing figure 13-4: i 2 c eeprom byte read s 1 0 1 0 a 10 a 9 a 8 0 r/~w control byte a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k a c k chip / block select bits s 1 0 1 0 0 control byte a c k a c k single byte addressing double byte addressing a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k address byte address low byte address high byte a 9 a 8 0 0 0 a 15 a 14 a 13 a 12 a 11 a 10 r/~w chip / block select bits s 1 0 1 0 a 10 a 9 a 8 control byte a c k s 1 0 1 0 control byte a c k single byte addressing read double byte addressing read 0 0 0 1 data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k p 1 data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k p a c k a c k r/~w chip / block select bits r/~w chip / block select bits downloaded from: http:///
lan9250 ds00001913a-page 286 ? 2015 microchip technology inc. figure 13-5 illustrates a typical i 2 c eeprom sequential byte reads for single and double byte addressing. sequential reads are used by the eeprom loader. refer to section 13.4, "eeprom loader" for additional information. for a register level description of a read operation, refer to section 13.3.7, "i2c master eeprom controller operation," on page 288 . 13.3.4 i 2 c eeprom byte writes following the device addressing, a data byte may be written to the eeprom by outputting the data after receiving the acknowledge from the eeprom. the data byte is acknowledged by the eeprom slave and the i 2 c master finishes the write cycle with a stop condition. if the eeprom slave fa ils to send an acknowledge, then the sequence is aborted (a start condition and a stop condition are sent) and the eeprom controller timeout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. following the data byte write cycle, the i 2 c master will poll the eeprom to determine when the byte write is finished. after meeting the minimum bus free time, a start condition is s ent followed by a control byte with a control code of 1010b, chip/block select bits low (since they are dont cares) and the r/~w bit low. if the eeprom is finished with the byte write, it will respond with an ackn owledge. otherwise, it will res pond with a no-acknowledge and the i 2 c master will issue a stop and repeat the poll. if the acknowledge does not occur within 30 ms, a timeout occurs (a start condition and a stop condition are sent) and the eeprom controller ti meout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. the check for timeout is only performed fo llowing each no-acknowledge, since it may be possible that the eeprom write fi nished before the timeout but the 30 ms expired before the po ll was performed (due to the bus being used by another master). once the i 2 c master receives the acknowledge, it concludes by sending a start condi tion, followed by a stop condition, which will place the eeprom into standby. figure 13-6 illustrates a typical i 2 c eeprom byte write. figure 13-5: i 2 c eeprom sequential byte reads figure 13-6: i 2 c eeprom byte write s 1 0 1 0 a 10 a 9 a 8 control byte a c k s 1 0 1 0 control byte a c k single byte addressing sequential reads 0 0 0 1 data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k p 1 data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k a c k a c k data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k p a c k data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k data byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 double byte addressing sequential reads ... r/~w chip / block select bits r/~w chip / block select bits ... a c k data byte p a c k s 1 0 1 0 0 r / ~w control byte chip / block select bits 0 0 0 s 1 0 1 0 0 r / ~w control byte chip / block select bits 0 0 0 s 1 0 1 0 0 r / ~w control byte chip / block select bits 0 0 0 ... d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k a c k a c k s p poll cycle poll cycle poll cycle data cycle conclude p p bus free time bus free time ... ... bus free time downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 287 lan9250 for a register level description of a write operation, refer to section 13.3.7, "i2c master eeprom controller operation," on page 288 . 13.3.5 wait state generation the serial clock is also used as an input as it can be held low by the slave devi ce in order to wait-state the data cycle. once the slave has data available or is ready to receive, it will release the clock. assuming the masters clock low time is also expired, the clock will rise and the cycle will continue. if the slave device holds the clock low for more than 30 ms, the current command sequence is aborted (a start condition and a stop condition are not sent since the clock is being held low, instead the clock and data lines are just released) and the eeprom controller timeout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. 13.3.6 i 2 c bus arbitration and clock synchronization since the i 2 c master and the i 2 c slave serial interfaces share common pins, there are at least two master i 2 c devices on the bus (the device and the host). there exists the potential that both masters try to a ccess the bus at the same time. the i 2 c specification handles this situation with three mechanisms: bus busy, clock synchronization and bus arbitration. note: the timing parameters referred to in the following subsec tions refer to the detailed timing information pre- sented in the nxp i 2 c-bus specification . 13.3.6.1 bus busy a master may start a transfer only if the bus is not busy. the bus is consid ered to be busy after the start condition and is considered to be free again t buf time after the stop condition. the standard mode value of 4.7 s is used for t buf since the eeprom master runs at the standard mode rate. fo llowing reset, it is unknown if the bus is actually busy, since the start condition may have been missed. therefore, following reset, the bus is initially considered busy and is considered free t buf time after the stop condition or if clock and data are seen high for 4 ms. 13.3.6.2 clock synchronization clock synchronization is used, since both masters may be g enerating different clock frequencies. when the clock is driven low by one master, each other active master will restart its low timer and also drive the clock low. each master will drive the clock low for its minimum low time and then rele ase it. the clock line will not go high until all masters have released it. the slowest master therefor e determines the actual low time. devices with shorter low timers will wait. once the clock goes high, each master will start its high timer. the first master to reach its high time will once again drive the clock low. the fastest master therefore determines the actu al high time. the process then repeats. clock synchroniza- tion is similar to the cycle stretching that can be done by a slave device, with the exceptio n that a slave device can only extend the low time of the clock. it c an not cause the falling edge of the clock. 13.3.6.3 arbitration arbitration involves testing the input data vs. the output data, when the clock goes high, to see if they match. since the data line is wired-anded, a master transmi tting a high value will see a mismatch if another master is transmitting a low value. the comparison is not done when receiving bits from t he slave. arbitration starts wit h the control byte and, if both masters are accessing the same slave, can continue into address and data bits (for writes) or acknowledge bits (for reads). if desired, a master that loses arbitration can continue to generate clo ck pulses until the end of the loosing byte (note that the ack on a read is consi dered the end of the byte) but the losing master may no longer drive any data bits. it is not permitted for another master to access the eeprom while the device is using it during startup or due to an eeprom command. the other mast er should wait sufficient time or poll the device to determine when the eeprom is available. this restriction simplifies the arbitration and access process since arbitration will always be resolved when transmitting the 8 control bits during the device addressing or during the poll cycles. if arbitration is lost during the device addressing, the i 2 c master will return to the beginning of the device addressing sequence and wait for the bus to become free. if arbitration is lost during a poll cycle, the i 2 c master will return to the beginning of the poll cycle sequence and wait for the bus to become free. note that in this case the 30 ms timeout-counter should not be reset. if the 30 ms timeout should expire while waiting for the bus to become free, the sequence should not abort without first completing a final poll (with the exception of the busy / arbitration timeout described in section 13.3.6.4 ). downloaded from: http:///
lan9250 ds00001913a-page 288 ? 2015 microchip technology inc. 13.3.6.4 timeout due to busy or arbitration it is possible for another master to monopolize the bus (due to a continual bu s busy or more successful arbitration). if successful arbitration is not achieved within 1.92 s from the star t of the read or write request or from the start of the poll cycle, the command sequence or poll cycle is aborted and the eeprom controller timeout (epc_timeout) bit in the eeprom command register (e2p_cmd) is set. note that this is a total timeout value and not the timeout for any one portion of the sequence. 13.3.7 i 2 c master eeprom co ntroller operation i 2 c master eeprom operations are performed using the eeprom command register (e2p_cmd) and eeprom data register (e2p_data) . the following operations are supported: read (read location) write (write location) reload (eeprom lo ader reload - see section 13.4, "eeprom loader" ) note: the eeprom loader uses the read command only. the supported commands are detailed in section 13.5.1, "eeprom command register (e2p_cmd)," on page 295 . details specific to each operational mode are explained in section 13.2, "i2c overview," on page 282 and section 13.4, "eeprom loader" , respectively. when issuing a write command, the desired data must first be written into the eeprom data register (e2p_data) . the write command may then be issued by setting the eeprom controller command (epc_command) field of the eeprom command register (e2p_cmd) to the desired command value. if the operation is a write, the eeprom controller address (epc_address) field in the eeprom command register (e2p_cmd) must also be set to the desired location. the command is executed when the eeprom controller busy (epc_busy) bit of the eeprom com- mand register (e2p_cmd) is set. the completion of the operation is indicated when the eeprom controller busy (epc_busy) bit is cleared. when issuing a read command, the eeprom controller command (epc_command) and eeprom controller address (epc_address) fields of the eeprom command register (e2p_cmd) must be configured with the desired command value and the read address, respectively. the read command is executed by setting the eeprom control- ler busy (epc_busy) bit of the eeprom command register (e2p_cmd) . the completion of the operation is indicated when the eeprom controller busy (epc_busy) bit is cleared, at which time the data from the eeprom may be read from the eeprom data register (e2p_data) . the reload operation is performed by writing the reload command into the eeprom controller command (epc_command) field of the eeprom command register (e2p_cmd) . the command is executed by setting the eeprom controller busy (epc_busy) bit of the eeprom command register (e2p_cmd) . in all cases, the software must wait for the eeprom controller busy (epc_busy) bit to clear before modifying the eeprom command register (e2p_cmd) . if an operation is attempted and the eeprom device does not respond within 30 ms, the device will timeout and the eeprom controller timeout (epc_timeout) bit of the eeprom command register (e2p_cmd) will be set. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 289 lan9250 figure 13-7 illustrates the process re quired to perform an eeprom read or write operation. figure 13-7: eeprom access flow diagram eeprom write idle write e2p_data register write e2p_cmd register read e2p_cmd register epc_busy = 0 eeprom read idle write e2p_cmd register read e2p_cmd register read e2p_data register epc_busy = 0 downloaded from: http:///
lan9250 ds00001913a-page 290 ? 2015 microchip technology inc. 13.4 eeprom loader the eeprom loader inte rfaces to the i 2 c eeprom controller, the phys and to the system csrs (via the register access mux). all system csrs are ac cessible to the eeprom loader. the eeprom loader runs upon a pin reset ( rst# ), power-on reset (por ), digital reset ( digital reset (digital_rst) bit in the reset control register (reset_ctl) ) or upon the issuance of a reload command via the eeprom com- mand register (e2p_cmd) . refer to section 6.2, "resets," on page 38 for additional information on resets. the eeprom contents must be loaded in a specific forma t for use with the eeprom loa der. an overview of the eeprom content format is shown in ta b l e 1 3 - 3 . each section of eeprom contents is discussed in detai l in the follow- ing sections. 13.4.1 eeprom loader operation upon a pin reset (( rst# ), power-on reset (por), digital reset ( digital reset (digital_rst) bit in the reset control register (reset_ctl) ) or upon the issuance of a reload command via the eeprom command register (e2p_cmd) , the eeprom controller busy (epc_busy) bit in the eeprom command register (e2p_cmd) will be set. while the eeprom loader is ac tive, the device ready (ready) bit of the hardware configuration register (hw_cfg) is cleared and no writes to the device should be attempted. the operational flow of the eeprom loader can be seen in figure 13-8 . table 13-3: eeprom cont ents format overview eeprom address description value 0 eeprom valid flag a5h 1 mac address low word [7:0] 1 st byte on the network 2 mac address low word [15:8] 2 nd byte on the network 3 mac address low word [23:16] 3 rd byte on the network 4 mac address low word [31:24] 4 th byte on the network 5 mac address high word [7:0] 5 th byte on the network 6 mac address high word [15:8] 6 th byte on the network 7 configuration strap values valid flag a5h 8 - 16 configuration strap values see table 13-4 17 burst sequence valid flag a5h 18 number of bursts see section 13.4.5, "register data" 19 and above burst data see section 13.4.5, "register data" downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 291 lan9250 figure 13-8: eeprom loader flow diagram byte 0 = a5h n digital_rst, rst# , por, reload y epc_busy = 1 read byte 0 read bytes 1-6 write bytes 1-6 into host mac address registers read byte 7-16 byte 7 = a5h y write bytes 8-16 into configuration strap registers load registers with current straps and restart phy auto-negotiation read byte 17 byte 17 = a5h do register data loop y load registers with current straps and restart phy auto-negotiation n epc_busy = 0 hmac reset byte 0 = a5h read bytes 1-6 write bytes 1-6 into host mac address registers y y epc_busy = 1 read byte 0 n n downloaded from: http:///
lan9250 ds00001913a-page 292 ? 2015 microchip technology inc. 13.4.2 eeprom valid flag following the release of rst# , por, digital_rst or a reload comm and, the eeprom loader starts by reading the first byte of data from the eeprom. if the value of a5h is not read from the first byte, the eeprom loader will load the current configuration strap values into the registers, restart phy auto-negotiation and then terminate, clearing the eeprom controller busy (epc_busy) bit in the eeprom command register (e2p_cmd) . otherwise, the eeprom loader will continue reading sequential bytes from the eeprom. 13.4.3 mac address the next six bytes in the eeprom, after t he eeprom valid flag, are written into the host mac address high register (hmac_addrh) and host mac address low register (hmac_addrl) registers. the eeprom bytes are written into the mac address registers in the order specified in table 13-3 . 13.4.3.1 host ma c address reload while the eeprom loader is in th e wait state, if a host mac reset is detected (via the host mac reset (hmac_rst) bit in the reset control register (reset_ctl) ), the eeprom loader will read byte 0. if the byte 0 value is a5h, the eeprom loader will read bytes 1 through 6 from the eeprom and reload the host mac address high register (hmac_addrh) and host mac address low register (hmac_addrl) . during this time, the epc_busy bit in the eeprom command register (e2p_cmd) is set and device ready (ready) bit of the hardware configuration reg- ister (hw_cfg) is cleared. 13.4.4 soft-straps the 7 th byte of data to be read from the eeprom is the configur ation strap values valid flag. if this byte has a value of a5h, the next 9 bytes of data (8-16) are written into t he configuration strap registers per the assignments detailed in table 13-4 . if the flag byte is not a5h, these next 9 bytes are skipped (they are still read to maintain the data burst, but are dis- carded). however, the current configurat ion strap values are still loaded into the registers and the phy auto-negotiation is still restarted. refer to section 7.0, "configuration straps," on page 54 for more information on configuration straps. note: bit locations in table 13-4 that do not define a configuration strap must be written as 0. table 13-4: eeprom configurati on bits b y t e / b i t765 4 321 0 byte 8 fd_fc_ strap_1 manual_ fc_strap_1 manual_m- dix_strap_1 auto_mdix- _strap_1 speed_ strap_1 duplex_ strap_1 autoneg_ strap_1 byte 9 byte 10 byte 11 led_fun_ strap[2] led_fun_ strap[1] led_fun_ strap[0] eee_ enable_ strap_1 byte 12 led_en_ strap[2] led_en_ strap[1] led_en_ strap[0] byte 13byte 14 hbi_ale_ qualifica- tion_strap hbi_rw_ mode_strap hbi_cs_ polarity_ strap hbi_rd_rd- wr_polarity_ strap hbi_wr_en_ polarity_ strap hbi_ale_ polarity_ strap byte 15byte 16 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 293 lan9250 13.4.5 register data optionally following the configuration strap values, the eeprom data may be formatted to allow access to the devices parallel, directly writable registers. access to indirectly accessible registers is achiev able with an appropriate sequence of writes (at the cost of eeprom space). this data is first preceded with a burst sequence valid flag ( eeprom byte 17). if this byte has a value of a5h, the data that follows is recognized as a sequence of bursts. otherwis e, the eeprom loader is finished, will go into a wait state and clear the eeprom controller busy (epc_busy) bit in the eeprom command register (e2p_cmd) . this can optionally generate an interrupt. the data at eeprom byte 18 and above should be formatted in a sequence of bursts. the first byte is the total number of bursts. following this is a series of bursts, each consisti ng of a starting address, count and the count x 4 bytes of data. this results in the following formula for formatting register data: 8 bits number_of_bursts repeat (number_of_bursts) 16 bits {starting_addre ss[9:2] / count[7:0]} repeat (count) 8 bits data[31:24], 8 bits data[23:16], 8 bits data[15:8], 8 bits data[7:0] note: the starting address is a dword address. appen ding two 0 bits will form the register address. as an example, the following is a 3 burst sequence, with 1, 2 and 3 dwords starting at register addresses 40h, 80h and c0h respectively: a5h, (burst sequence valid flag) 3h, (number_of_bursts) 16{10h, 1h}, (starting_address1 divided by 4 / count1) 11h, 12h, 13h, 14h, (4 x count1 of data) 16{20h, 2h}, (starting_address2 divided by 4 / count2) 21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h, (4 x count2 of data) 16{30h, 3h}, (starting_address3 divided by 4 / count3) 31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 3ah, 3bh, 3ch (4 x count3 of data) in order to avoid overwriting the mac csr or mii managemen t interfaces, the eepr om loader waits until the following bits are cleared before performing any register write: host mac csr busy (hmac_csr_busy) bit of the host mac csr interface command register (mac_cs- r_cmd) mii busy (miibzy) bit of the host mac mii access register (hmac_mii_acc) the eeprom loader checks that the eeprom address space is not exceeded. if so, it will stop and set the eeprom loader address overflow (loader_overflow) bit in the eeprom command register (e2p_cmd) . the address limit is based on the eeprom_size_strap which specifies a range of sizes. the ad dress limit is set to the largest value of the specified range. 13.4.6 eeprom loader finished wait-state once finished with the last burst, the eeprom loader will go into a wait-state and the eeprom controller busy (epc_busy) bit of the eeprom command register (e2p_cmd) will be cleared. this can optionally generate an inter- rupt. downloaded from: http:///
lan9250 ds00001913a-page 294 ? 2015 microchip technology inc. 13.5 i 2 c master eeprom controller registers this section details the directly addressable i 2 c master eeprom controller relat ed system csrs. these registers should only be used if an eeprom has been connect ed to the device. for an overview of the entire directly addressable register map, refer to section 5.0, "regist er map," on page 29 . table 13-5: i 2 c master eeprom controller registers address register name (symbol) 1b4h eeprom command register (e2p_cmd) 1b8h eeprom data register (e2p_data) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 295 lan9250 13.5.1 eeprom command re gister (e2p_cmd) this read/write r egister is used to control the read and write operatio ns of the serial eeprom. offset: 1b4h size: 32 bits bits description type default 31 eeprom controller busy (epc_busy) when a 1 is written into this bit, th e operation specified in the epc_com- mand field of this register is perfor med at the specified eeprom address. this bit will remain set until the selected operation is complete. in the case of a read, this indicates that the host can read valid data from the eeprom data register (e2p_data) . the e2p_cmd and e2p_data registers should not be modified until this bit is cleared. in the case where a write is attempted and an eeprom is not present, the epc_busy bit remains set until the eeprom controller timeout (epc_timeout) bit is set. at this time the epc_busy bit is cleared. note: epc_busy is set immediately following power-up, or pin reset, or digital_rst reset. this bit is also set following the setting of the host mac reset (hmac_rst) bit in the reset contro l register (reset_ctl) . after the eeprom loader has finished loading, the epc_busy bit is cleared . refer to chapter section 13.4, "eeprom loader," on page 290 for more information. r/w sc 0b downloaded from: http:///
lan9250 ds00001913a-page 296 ? 2015 microchip technology inc. 30:28 eeprom controller co mmand (epc_command) this field is used to issue commands to the eeprom controller. the eeprom controller will execute a command when the epc_busy bit is set. a new command must not be issued until the previous command completes. the field is encoded as follows: note: only the read, write and reload commands are valid for i 2 c mode. if an unsupported command is attempted, the epc_busy bit will be cleared and epc_timeout will be set. the eeprom operations are defined as follows: read (read location) this command will cause a read of the eeprom location pointed to by the epc_ad- dress bit field. the result of the read is available in the eeprom data register (e2p_data) . write (write location) if erase/write operations are enabled in t he eeprom, this command will cause the contents of the eeprom data register (e2p_data) to be written to the eeprom location selected by the epc_address field. reload (eeprom loader reload) instructs the eeprom loader to reload the device from the eeprom. if a value of a5h is not found in the first address of the eeprom, the eeprom is assumed to be un-programmed and the reload operation will fail. the cfg_loaded bit indicates a successful load. following this command, the device will enter the not ready state. the device ready (ready) bit in the hardware configuration register (hw_cfg) should be polled to determine then the reload is complete. r/w 000b 27:19 reserved ro - 18 eeprom loader address over flow (loader_overflow) this bit indicates that the eeprom loade r tried to read past the end of the eeprom address space. this indica tes misconfigured eeprom data. this bit is cleared when the eeprom loader is restarted with a reload command, host mac reset (hmac_r eset), or a digital reset (digi- tal_rst). ro 0b bits description type default [30] [29] [28] operation 000 r e a d 0 0 1 reserved 0 1 0 reserved 011 w r i t e 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 111 r e l o a d downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 297 lan9250 13.5.2 eeprom data register (e2p_data) this read/write register is used in conjunction with the eeprom command register (e2p_cmd) to perform read and write operations with the serial eeprom. 17 eeprom controller ti meout (epc_timeout) this bit is set when a timeout occurs, indicating the last operation was unsuc- cessful. if an eeprom write operation is performed and no response is received from the eeprom within 30 ms, the eeprom controller will time- out and return to its idle state. this bit is also set if the eeprom fail s to respond with t he appropriate acks, if the eeprom slave device holds the cl ock low for more than 30 ms, if the i2c bus is not acquired within 1.92 seconds , or if an unsupported epc_command is attempted. this bit is cleared when written high. r/wc 0b 16 configuration loaded (cfg_loaded) when set, this bit indicates that a valid eeprom was found and the eeprom loader completed normally. this bit is set upon a successful load. it is cleared on power-up, pin and digital_rst resets, host mac reset (hmac_reset), or at the start of a reload. this bit is cleared when written high. r/wc 0b 15:0 eeprom controller address (epc_address) this field is used by the eeprom contro ller to address a specific memory location in the serial eeprom. this address mu st be byte aligned. r/w 0000h offset: 1b8h size: 32 bits bits description type default 31:8 reserved ro - 7:0 eeprom data (eeprom_data) this field contains the data read from or written to the eeprom. r/w 00h bits description type default downloaded from: http:///
lan9250 ds00001913a-page 298 ? 2015 microchip technology inc. 14.0 ieee 1588 14.1 functional overview the device provides hardware support for the ieee 1588-2008 precision time protocol (ptp), allowing clock synchro- nization with remote ethernet de vices, packet time stamping, and time driven event generation. note: support for the ieee 1588 -2002 (v1) packet format is not provided. the device may function as a master or a slave clock per the ieee 1588-2008 specific ation. end-to-end and peer-to- peer link delay mechanisms are supported as are one-step and two-step operations. a 32-bit seconds and 30-bit nanoseconds tunable clock is prov ided that is used as the time source for all ptp timestamp related functions. a 1588 clock events sub-module provi des 1588 clock comparison based interrupt generation and timestamp related gpio event generation. gpio pins can be used to trig ger a timestamp capture when configured as an input, or output a signal based on a 1588 clock target compare event. all features of the ieee 1588 unit can be monitored and configured via their respective configuration and status regis- ters. a detailed description of all 1588 csrs is included in section 14.8, "1588 registers" . 14.1.1 ieee 1588-2008 ieee 1588-2008 specifies a precision time protocol (ptp) used by master and slave clock devices to pass time infor- mation in order to achieve clock synchroniza tion. ten network message types are defined: sync follow_up delay_req delay_resp pdelay_req pdelay_resp pdelay_resp_follow_up announce signaling management the first seven message types are used for clock synchronization. using these messages, the protocol software may calculate the offset and network delay between timestamps, adjusting the slave clock frequency as needed. refer to the ieee 1588-2008 pr otocol for message definit ions and proper usage. a ptp domain is segmented into ptp sub-domains, which ar e then segmented into ptp communication paths. within each ptp communication path there is a ma ximum of one master clock, which is th e source of time for each slave clock. the determination of which clock is the master and which cl ock(s) is(are) the slave(s) is not fixed, but determined by the ieee 1588-2008 protocol. similarly, each ptp sub-domain may have only one master clock, referred to as the grand master clock. ptp communication paths are conceptually equivalent to et hernet collision domains and may contain devices which extend the network. however, unlike et hernet collision domains, the ptp commun ication path does not stop at a net- work switch, bridge, or router. this leads to a loss of prec ision when the network switch/bridge/router introduces a vari- able delay. boundary clocks are defined which conceptually by pass the switch/bridge/router (either physically or via device integration). essentially, a boundary clock acts as a sl ave to an upstream master, and as a master to a down stream slave. a boundary clock may contain multiple ports, but a maximum of one slave port is permitted. although boundary clocks solve the issue of the variable delay influencing the synchronization accuracy, they add clock jitter as each boundary clock tracks the clock of its upstream master. another approach that is supported is the concept of transparent clocks. these devices measure the delay they ha ve added when forwarding a message (the residence time) and report this additional delay either in the forw arded message (one-step) or in a subsequent message (two- step). the ptp relies on the knowledge of the path delays between t he master and the slave. with this information, and the knowledge of when the master has sent the packet, a slave can calculate its clock offset from the master and make appropriate adjustments. there are two methods of obtaining the network path delay. using the end-to-end method, packets are exchanged between the slave and the master. an y intermediate variable bridge or switch delays are com- pensated by the transparent clock method described above. us ing the round trip time and accounting for the residence time reported, the slave can calculate the mean delay fr om the master. each slave sends and receives its own mes- downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 299 lan9250 sages and calculates its own delay. while the end-to-end method is the simplest, it does add burden on the master since the master must process packets from each slave in the system. this is ampl ified when bou ndary clocks are replaced by transparent clocks. also, the end-to-e nd delays must be recalculated if ther e is a change in the network topology. using the peer-to-peer method, packets are exchanged only be tween adjacent master, slaves and transparent clocks. each peer pair calculates the receive path delay. as time synchronization packets are forwarded between the master and the slave, the transparent clock adds the pre-measured receive path delay into the residence time. the final receiver adds its receive path delay. using the peer-to-peer method, the full path delay is accounted for without the mas- ter having to service each slave. the peer-to-peer method better supports network topo logy changes since each path delay is kept up-to-date re gardless of the port status. the ptp implementation consists of the following major function blocks: ptp timestamp this block provides time stamping and packet modification functions. 1588 clock this block provides a tunable clock that is used as the time source for all ptp timestamp related functions. 1588 clock events this block provides clock comparison-based interrupt generation and timestamp related gpio event generation. 1588 gpios this block provides for time stamping gpio input events and for outputting clock comparison-based interrupt sta- tus. 1588 interrupt this block provides interrupt generation, masking and status. 1588 registers this block provides contains all configuration, control and status registers. downloaded from: http:///
lan9250 ds00001913a-page 300 ? 2015 microchip technology inc. 14.2 ptp timestamp this sub-module handles all ptp packet tasks related to reco rding timestamps of packets and inserting timestamps into packets. modes supported are: ordinary clock, master and slave, one-step and two-step, end-to-end or peer-to-peer delay - all 1588 packets are to and from the host mac - rx and tx timestamps saved in registers for s/w - rx timestamp stored in packet for ease of retrieval by s/w - egress timestamp of sync packet inserted on-the-fly for one-step - tx timestamp of delay_req packe t stored in received delay_resp packet for ease of retrieval - correction field and ingress timestamp of pdelay_req packet saved in registers for one-step turnaround time - correction field of pdelay_resp packet automaticall y calculated and inserted on-the-fly for one-step - ptp checksums and ethernet fcs updated on-the-fly - ingress and egress timestamps corrected for latency - asymmetry corrections - peer delay correction on received sync packets functions include: detecting a ptp packet - 802.3/snap or ethernet ii encoding - skipping over vlan tags - ethernet, ipv4 or ipv6 message formats - skipping over ip extension headers - checking the mac and / or the ip addresses recording the timestamp of received packets into registers - accounting for the ingress latency recording the timestamp of received packets into the packet and updating the layer 3 checksu m and layer 2 fcs fields - accounting for the ingress latency forwarding or filtering ptp packets as needed to support ordinary clock mode recording the timestamp of transmitted packets into registers - accounting for the egress latency one-step on-the-fly timestamp insertion for sync packets and updating the layer 3 checksum and layer 2 fcs one-step on-the-fly turnaround time insertion for pdelay_req packets and updating the layer 3 checksum and layer 2 fcs note: support for the ieee 1588 -2002 (v1) packet format is not provided. 14.2.1 receive frame processing 14.2.1.1 ingress time snapshot for each ethernet frame, the receive frame processing detects the sfd field of the frame and temporarily saves the current 1588 clock value. ingress latency the ingress latency is the amount of time between the star t of the frames first symbol after the sfd on the network medium and the point when the 1588 clock value is internally captured. it is specified by the rx latency (rx_la- tency[15:0]) field in the 1588 port latency register (1588_latency) and is subtracted from the 1588 clock value at the detection of the sfd. the setting is used to adjust t he internally captured 1588 clock value such that the resultant timestamp more accurately corresponds to the start of t he frames first symbol after the sfd on the network medium. the ingress latency consists of the receive latency of the ph y and the latency of the 1588 frame detection circuitry. the value depends on the port mode. typical values are: downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 301 lan9250 100base-tx: 285ns 100base-fx: 231ns plus the receive latency of the fiber transceiver 10base-t: 1674ns 14.2.1.2 1588 receive parsing the 1588 receive parsing block parses the incoming frame to identify 1588 ptp messages. note: support for the ieee 1588 -2002 (v1) packet format is not provided. the receive parsing block may be programmed to detect ptp messages encoded in udp/ ipv4, udp/ipv6 and layer 2 ethernet formats via the rx ipv4 enable (rx_ipv4_en) , rx ipv6 enable (rx_ipv6_en) and rx layer 2 enable (rx_layer2_en) bits in the 1588 port rx parsing configurati on register (1588_rx_parse_config) . vlan tagged and non-vlan tagged frame formats are support ed. multiple vlan tags are handled as long as they all use the standard type of 0x8100. both ethernet ii (type fiel d) and 802.3 (length field) w/ snap frame formats are sup- ported. the following tests are made to determine that the packet is a ptp message. mac destination address checking is enabled via the rx mac address enable (rx_mac_addr_en) in the 1588 port rx parsing configuration register (1588_rx_parse_config) . for the layer 2 message format, the addresses of 01:1 b:19:00:00:00 or 01:80:c2: 00:00:0e may be enabled via the 1588 port rx parsing configuration register (1588_rx_parse_config) . either address is allowed for peer delay and non-peer delay messages. for ipv4/udp messages, any of the iana assigned multicast ip destination addresses for ieee 1588 (224.0.1.129 and 224.0.1.130 through .132), as well as the ip destination address for the peer delay mechanism (224.0.0.107) may be enabled via the 1588 port rx parsing configuration register (1588_rx_parse_con- fig) . these ip addresses map to the 802.3 mac addresses of 01:00:5e:00:01:81 through 01:00:5e:00:01:84 and 01:00:5e:00:00:6b. any of these addresses are allowed for peer delay and non-peer delay messages. for ipv6/udp messages, any of the iana assigned multicast ip destination addresses for ieee 1588 (ff0x:0:0:0:0:0:0:181 and ff0x:0:0:0:0:0:0:182 through : 184), as well as the ip destination address for the peer delay mechanism (ff02:0:0:0:0: 0:0:6b) may be enabled via the 1588 port rx parsing configuration register (1588_rx_parse_config) . these ip addresses map to the 802. 3 mac addresses of 33:33:00:00:01:81 through 33:33:00:00:01: 84 and 33:33:00:00:00:6b. any of these addr esses are allowed for peer delay and non- peer delay messages. a user defined mac address defined in the 1588 user mac address high-word register (1588_us- er_mac_hi) and the 1588 user mac address low-dwo rd register (1588_user_mac_lo) may also be indi- vidually enabled for the above formats. if the type / length field indicates an ethertype then for the layer 2 message format, the ethertype must equal 0x88f7. for ipv4/udp messages, the ethertype must equal 0x0800. for ipv6/udp messages, the ethertype must equal 0x86dd. if the type / length field indicates a length and the next 3 bytes equal 0xaaaa03 (indicating that a snap header is present) and the snap header has a oui equal to 0x000000 then for the layer 2 message format, the ethertype in the snap header must equal 0x88f7. for ipv4/udp messages, the ethertype in the snap header must equal 0x0800. for ipv6/udp messages, the ethertype in the snap header must equal 0x86dd. for ipv4/udp messages, the version field in the ipv4 header must equal 4, the ihl field must be 5 and the proto- col field must equal 17 (udp) or 51 (ah). ipv4 options are not supported. for ipv6/udp messages, the version field in the ipv6 hea der must equal 6 and the next header field must equal 17 (udp) or one of the ipv6 extension header values (0 - hop-by-hop options, 60 - destination options, 43 - downloaded from: http:///
lan9250 ds00001913a-page 302 ? 2015 microchip technology inc. routing, 44 - fragment, 51 - authentication header (ah) for ipv4/udp messages, destination ip address checking is enabled via the rx ip address enable (rx_ip_ad- dr_en) in the 1588 port rx parsing configuration register (1588_rx_parse_config) . any of the iana assigned multicast ip destination addresses for ieee 1588 ( 224.0.1.129 and 224.0.1.130 through .132), as well as the ip destination address for the peer dela y mechanism (224.0.0.107) may be enabled via the 1588 port rx parsing configuration register (1588_rx_parse_config) . any of these addresses are allowed for peer delay and non-peer delay messages. for ipv6/udp messages, destination ip address checking is enabled via the rx ip address enable (rx_ip_ad- dr_en) in the 1588 port rx parsing configuration register (1588_rx_parse_config) . any of the iana assigned multicast ip destination addresses for ieee 1588 (ff0x:0:0:0:0:0:0:181 and ff0x:0:0:0:0:0:0:182 through :184), as well as the ip destination address for the peer delay mechanism (f f02:0:0:0:0:0:0:6b) may be enabled via the 1588 port rx parsing configuratio n register (1588_rx_parse_config) . any of these addresses are allowed for peer delay and non-peer delay messages. for ipv4/udp if the protocol field in the fixed header wa s 51 (ah), the next header field is checked for 17 (udp) and the ah header is skipped. for ipv6/udp if the next header field in the fixed hea der was one of the ipv6 extens ion header values, the next header field in the extension header is checked for 17 (udp) or one of the ipv6 extension header values. if it is one of the ipv6 extension header values, the process repeats until either a value of 17 (udp) or a value of 59 (no next header) are found or the packet ends. 14.2.1.3 receive message ingress time recording following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked for all of the following. the messagetype field of the ptp header is checked and only those messages enabled via the rx ptp mes- sage type enable (rx_ptp_message_en[15:0]) bits in the 1588 port rx timestamp configuration register (1588_rx_timestamp_config) will be have their ingress times saved. typically sync, delay_req, pde- lay_req and pdelay_resp messages are enabled. the versionptp field of the ptp header is checked against the rx ptp version (rx_ptp_version[3:0]) field in the 1588 port rx timestamp configuration register (1588_rx_timestamp_config) . only those messages with a matching version will be have their ingress ti mes saved. a setting of 0 allows any ptp version. note: support for the ieee 1588 -2002 (v1) packet format is not provided. if enabled via the rx ptp domain match en able (rx_ptp_domain_en) bit in the 1588 port rx timestamp configuration register ( 1588_rx_timestamp_config) , the domainnumber field of the ptp header is checked against the rx ptp domain (r x_ptp_domain[7:0]) value in the same register. only those messages with a matching domain will be have their ingress times saved. if enabled via the rx ptp alternate master en able (rx_ptp_alt_master_en) bit in the 1588 port rx time- stamp configuration register (1588_rx_timestamp_config) , the alternatemasterflag in the flagfield of the ptp header is checked and only those messages with an alternatemasterflag set to 0 will be have their ingress times saved. at the end of the frame, the frames fc s and the udp checksum (for ipv4 and ipv6 formats) are verified. fcs checking can be disabled using the rx ptp fcs check dis able (rx_ptp_fcs_dis) bit in the 1588 port rx timestamp con- figuration register (1588_rx_timestamp_config) . udp checksum checking c an be disabled using the rx ptp udp checksum check disable (rx_ptp_udp_chksum_dis) bit in the same register. note: a ipv4 udp checksum value of 0x00 00 indicates that the checksum is not included and is considered a pass. a ipv6 udp checksum value of 0x0000 is invalid and is considered a fail. note: for ipv6, the udp checksum calculatio n includes the ipv6 pseudo heade r. part of the ipv6 pseudo header is the final ipv6 destination address. if the ipv6 packet does not contain a routing header, t hen the final ipv6 destination address is the destina- tion address contained in the ipv6 header. if the ipv6 packet does contain a routing header, then the final ipv6 destination address is the address in the last element of the routing header. note: the udp checksum is calculated over the entire udp payload as indicat ed by the udp length field and not the assumed ptp packet length. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 303 lan9250 note: the udp checksum calculation does not included layer 2 pad bytes, if any. if the fcs and checksum tests pass: the latency adjusted, 1588 clock value, saved above at the start of the frame, is recorded into the 1588 port rx ingress time seconds register (1588_rx_ingress_sec) and 1588 port rx ingress time nanoseconds reg- ister (1588_rx_ingress_ns) . the messagetype and sequenceid fields and 12-bit crc of t he portidentity field of the ptp header are recorded into the message type (msg_type) , sequence id (seq_id) and source port identity crc (src_prt_crc) fields of the 1588 port rx message header register (1588_rx_msg_header) . the 12-bit crc of the portidentity field is created by using the polynomial of x 12 + x 11 + x 3 + x 2 + x + 1. the corresponding maskable 1588 rx timestamp interrupt (1588_rx_ts_int) is set in the 1588 interrupt status register (1588_int_sts) . up to four receive events are saved per port with the count shown in the 1588 rx timestamp count (1588_rx- _ts_cnt[2:0]) field in the 1588 port capture information register (1588_cap_info) . additional events are not recorded. when the appropriate 1588 rx timestamp interrupt (1588_rx_ts_int) bit is written as a one to clear, 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) will decrement. if there are remaini ng events, the capture registers will update to the next event and the interrupt will set again. pdelay_req ingress time saving one-step pdelay_resp messages sent by t he host, require their correctionfield to be calculated on-the-fly to include the turnaround time between the ingress of the p delay_req and the egress time of the pdelay_resp. the 1588 port rx pdelay_req ingress time seconds register (1588_rx_pdreq_sec) and the 1588 port rx pde- lay_req ingress time nanoseconds register (1588_rx_pdreq_ns) hold the ingress time of the pdelay_req mes- sage. the 1588 port rx pdelay_req ingress correctio n field high register (1588_rx_pdreq_cf_hi) and the 1588 port rx pdelay_req ingress correction field low register (1588_rx_pdreq_cf_low) hold the correctionfield of the pdelay_req message. these registers can be set by s/w prio r to sending the pdelay_resp message. alternatively, these registers can be updated by the h/w when the pdelay_req me ssage is received. this function is enabled by the auto update (auto) bit in the 1588 port rx pdelay_req ingress time nanoseconds register (1588_rx_pdreq_ns) independent from the rx ptp message type enable (rx_ptp_message_en[15:0]) bits. as above (including all applicable notes): the versionptp and domainnumber fields and alternat emasterflag in the flagfield of the ptp header are checked, if enabled. note: support for the ieee 1588 -2002 (v1) packet format is not provided. at the end of the frame, the frames fcs and the udp ch ecksum (for ipv4 and ipv6 formats) are verified, if enabled. if all tests pass, then the pdelay_req message information is updated. 14.2.1.4 ingress pa cket modifications ingress time insertion into packets as an alternate to reading the receive time stamp from regi sters and matching it to the correct frame received in the host mac, the saved, latency adjusted, 15 88 clock value can be stored into the packet. this function is enabled via the rx ptp insert timestamp enable (rx_ptp_insert_ts_en) and rx ptp insert timestamp seconds enable (rx_ptp_insert_ts_sec_en) bits in the 1588 port rx timestamp insertion configu- ration register (1588_rx_ts_insert_config) . note: inserting the ingress time into the packet is an addi tional, separately enabled, feature verses the ingress time recording described above. the capture registers are still updated as is the appropriate 1588 rx timestamp interrupt (1588_rx_ts_int) bit and the 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) field. following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked for all of the following. the messagetype field of the ptp header is checked and only those messages enabled via the rx ptp mes- downloaded from: http:///
lan9250 ds00001913a-page 304 ? 2015 microchip technology inc. sage type enable (rx_ptp_message_en[15:0]) bits in the 1588 port rx timestamp configuration register (1588_rx_timestamp_config) will be have their ingress times inserted. typically sync, delay_req, pde- lay_req and pdelay_resp messages are enabled. the versionptp field of the ptp header is checked against the rx ptp version (rx_ptp_version[3:0]) field in the 1588 port rx timestamp configuration register (1588_rx_timestamp_config) . only those messages with a matching version will be have their ingress times inserted. a setting of 0 allows any ptp version. note: support for the ieee 1588 -2002 (v1) packet format is not provided. note: the domainnumber field and alternatemasterflag in the flagfield of the ptp header are not tested for pur- pose of ingress time insertion. the packet is modified as follows: the four bytes of nanoseconds are stored at an offset from the start of the ptp header the offset is specified in rx ptp insert timestamp offset (rx_ptp_insert_ts_offset[5:0]) field in the 1588 port rx timestamp insertion configurat ion register (1588_rx_ts_insert_config) . the lowest two bits of the seconds are stor ed into the upper 2 bits of the nanoseconds. if also enabled, bits 3:0 of the seconds are stored into bi ts 3:0 of a reserved byte in the ptp header. bits 7:4 are set to zero. the offset of this reserved byte is specified by the rx ptp insert timestamp seconds offset (rx_pt- p_insert_ts_sec_offset[5:0]) field in the 1588 port rx timestamp insert ion configuration register (1588_rx_ts_insert_config) . note: for version 2 of ieee 1588, the four reserved byte s starting at offset 16 should be used for the nanosec- onds. the reserved byte at offset 5 should be used for the seconds. delay request egress time insertion into delay reponse packet normally, in ordinary clock operation, the egress times of transmitted delay_req packets are saved and read by the host s/w. to avoid the need to read these timestamps via register access, the egress time of the last transmitted delay_req packet on the port can be inserted into delay_resp packets received on the port. this function is enabled via the rx ptp insert delay request egress in delay response enable (rx_pt- p_insert_dreq_dresp_en) bit in the 1588 port rx timestamp insertion configuration register (1588_rx- _ts_insert_config) . as with any ingress time insertion, delay_resp messages must be enable in the 1588 port rx timestamp configura- tion register (1588_rx_timestamp_config) and the rx ptp insert timestamp enable (rx_pt- p_insert_ts_en) must be set. note: inserting the delay request egress time into the packet is an additional, separately enabled, feature verses the egress time recording described above. as with ingress time insertion into packets , above: the versionptp field of the ptp header is checked a nd the domainnumber field and alternatemasterflag in the flagfield of the ptp header are not checked. note: support for the ieee 1588 -2002 (v1) packet format is not provided. the four bytes of nanoseconds / 2 bits of seconds are stored at the specified offset of the ptp header. bits 3:0 of the seconds are stored at the sp ecified offset in the ptp header, if enabled. effectively, this function is the same as the ingress time insertion into packets except that the egress time of the delay_req is inserted instead of the ingress time of the delay_resp. frame updating frames are modified even if their original fcs or udp checksum is invalid. for ipv4, the udp checksum is set to 0. if the original udp checksum was invalid, a receive symbol error is forced and the 1588 port rx checksum dropped count register (1 588_rx_chksum_dropped_cnt) incremented. this can be disabled by the rx ptp bad udp checksum force erro r disable (rx_ptp_bad_udp_chksum_- downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 305 lan9250 force_err_dis) field in the 1588 port rx timestamp insertion configuration register (1588_rx- _ts_insert_config) . note: an original udp checksum value of 0x0000 indica tes that the checksum is no t included and is considered a pass. note: the original udp checksum is calculated over the ent ire udp payload as indicated by the udp length field and not the assumed ptp packet length. note: the original udp checksum ca lculation does not included layer 2 pad bytes, if any. for ipv6, the two bytes beyond the end of the ptp messa ge are modified so that th e original udp checksum is correct for the modified payload. these bytes are updated by accumulating the differences between the original frame data and the substituted data usin g the mechanism defined in ietf rfc 1624. if the original udp checksum was invalid, a receive symbol error is forced and the 1588 port rx checksum dropped count register (1 588_rx_chksum_dropped_cnt) incremented. this can be disabled by the rx ptp bad udp checksum force erro r disable (rx_ptp_bad_udp_chksum_- force_err_dis) field in the 1588 port rx timestamp insertion configuration register (1588_rx- _ts_insert_config) . note: since the two bytes beyond the end of the ptp message are modified based on the differences between the original frame da ta and the substituted data, an invalid incoming checksum would always result in an outgoing checksum error. note: an original udp checksum value of 0x0000 is invalid and is considered a fail. note: for ipv6, the udp checksum calculation includes the ipv6 ps eudo header. pa rt of the ipv6 pseudo header is the final ipv6 destination address. if the ipv6 packet does not contain a routing header, t hen the final ipv6 destination address is the destina- tion address contained in the ipv6 header. if the ipv6 packet does contain a routing header, then the final ipv6 destination address is the address in the last element of the routing header. note: the original udp checksum is calculated over the ent ire udp payload as indicated by the udp length field and not the assumed ptp packet length. note: the original udp checksum ca lculation does not included layer 2 pad bytes, if any. note: the two bytes beyond the end of the ptp message are located by using the messagelength field from the ptp header. the frame fcs is recomputed. if the original fcs was invalid, a bad fcs is forced. if the frame has a receive symbol error(s), a receive symbol error indication will be propagated at the same nibble location(s). note: fcs and udp checksums are only up dated if the frame was actually m odified. if no modifications are done, the existing fcs and checksums are left unchanged. 14.2.1.5 ingress me ssage filtering ptp messages can be filtered upon receive. following the det ermination of packet format and qualification of the packet as a ptp message above, the ptp heade r is checked for any of the following. the messagetype field of the ptp header is checked and those messages that have their rx ptp message type filter enable (rx_pt p_msg_fltr_en[15:0]) bits in the 1588 port rx filter config uration register (1588_rx_- filter_config) set will be filtered. typically delay_req and delay_resp messages are filtered in peer-to-peer transparent clocks. the versionptp field of the ptp header is checked against the rx ptp version (rx_ptp_version[3:0]) field in the 1588 port rx timestamp configuration register (1588_rx_timestamp_config) . if the rx ptp version filter enable (rx_pt p_version_fltr_en) bit in the 1588 port rx filter configuration register (1588_rx_- filter_config) is set, messages with a non-matching version will be filtered. a version setting of 0 allows any ptp version and would not cause filtering. note: support for the ieee 1588 -2002 (v1) packet format is not provided. downloaded from: http:///
lan9250 ds00001913a-page 306 ? 2015 microchip technology inc. if enabled via the rx ptp domain filter enab le (rx_ptp_domain_fltr_en) bit in the 1588 port rx filter configuration register (1588_rx_filter_config) , messages whose domainnumber field in the ptp header does not match the rx ptp domain (rx_ptp_domain[7:0]) value in the 1588 port rx timestamp configura- tion register (1588_rx_timestamp_config) will be filtered. if enabled via the rx ptp alternate master filter e nable (rx_ptp_alt_master_fltr_en) bit in the 1588 port rx filter configuration regi ster (1588_rx_filter_config) , messages whose alternatemasterflag in the flag- field of the ptp header is set will be filtered. at the end of the frame, the frames fc s and the udp checksum (for ipv4 and ipv6 formats) are verified. fcs checking can be disabled using the rx ptp fcs check dis able (rx_ptp_fcs_dis) bit in the 1588 port rx timestamp con- figuration register (1588_rx_timestamp_config) . udp checksum checking c an be disabled using the rx ptp udp checksum check disable (rx_ptp_udp_chksum_dis) bit in the same register. note: a ipv4 udp checksum value of 0x00 00 indicates that the checksum is not included and is considered a pass. a ipv6 udp checksum value of 0x0000 is invalid and is considered a fail. note: for ipv6, the udp checksum calculatio n includes the ipv6 pseudo heade r. part of the ipv6 pseudo header is the final ipv6 destination address. if the ipv6 packet does not contain a routing header, t hen the final ipv6 destination address is the destina- tion address contained in the ipv6 header. if the ipv6 packet does contain a routing header, then the final ipv6 destination address is the address in the last element of the routing header. note: the udp checksum is calculated over the entire udp payload as indicat ed by the udp length field and not the assumed ptp packet length. note: the udp checksum calculation does not included layer 2 pad bytes, if any. if the fcs and checksum tests pass, the frame is f iltered by insert ing a receive symbol error and the 1588 port rx fil- tered count register (1588_rx_filtered_cnt) is incremented. note: the mac will count this as an errored packet. note: message filtering is an additional, separately enabled , feature verses any packet ingress time recording and packet modification. although these functions typically would not be used together on the same message type. 14.2.2 transmit frame processing 14.2.2.1 egress time snapshot for each ethernet frame, the transmit frame processing det ects the sfd field of the frame and temporarily saves the current 1588 clock value. egress latency the egress latency is the amount of time between the point when the 1588 clock value is internally captured and the start of the frames first symbol after the sfd on the network medium. it is specified by the tx latency (tx_la- tency[15:0]) field in the 1588 port latency register (1588_latency) and is added to the 1588 clock value at the detection of the sfd. the setting is used to adjust the inter nally captured 1588 clock value such that the resultant time- stamp more accurately corresponds to the start of the fr ames first symbol after the sfd on the network medium. the egress latency consists of the transmit latency of the ph y and the latency of the 1588 frame detection circuitry. the value depends on the port mode. typical values are: 100base-tx: 95ns 100base-fx: 68ns plus the transmit latency of the fiber transceiver 10base-t: 1139ns 14.2.2.2 1588 transmit parsing the 1588 transmit parsing block parses the outgoing frame to identify 1588 ptp messages. note: support for the ieee 1588 -2002 (v1) packet format is not provided. the transmit parsing block may be programmed to detect ptp messages encoded in udp/ipv4, udp/ipv6 and layer 2 ethernet formats via the tx ipv4 enable (tx_ipv4_en) , tx ipv6 enable (tx_ipv6_en) and tx layer 2 enable (tx_layer2_en) bits in the 1588 port tx parsing configuratio n register (1588_tx_parse_config) . downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 307 lan9250 vlan tagged and non-vlan tagged frame formats are support ed. multiple vlan tags are handled as long as they all use the standard type of 0x8100. both ethernet ii (type fiel d) and 802.3 (length field) w/ snap frame formats are sup- ported. the following tests are made to determine that the packet is a ptp message. mac destination address checking is enabled via the tx mac address enable (tx_mac_addr_en) in the 1588 port tx parsing configurati on register (1588_tx_parse_config) . for the layer 2 message format, the addresses of 01:1 b:19:00:00:00 or 01:80:c2: 00:00:0e may be enabled via the 1588 port tx parsing configurati on register (1588_tx_parse_config) . either address is allowed for peer delay and non-peer delay messages. for ipv4/udp messages, any of the iana assigned multicast ip destination addresses for ieee 1588 (224.0.1.129 and 224.0.1.130 through .132), as well as the ip destination address for the peer delay mechanism (224.0.0.107) may be enabled via the 1588 port tx parsing configuration register (1588_tx_parse_config) . these ip addresses map to the 802.3 mac addresse s of 01:00:5e:00:01:81 th rough 01:00:5e:00:01:84 and 01:00:5e:00:00:6b. any of these addresses are allowed for peer delay and non-peer delay messages. for ipv6/udp messages, any of the iana assigned multicast ip destination addresses for ieee 1588 (ff0x:0:0:0:0:0:0:181 and ff0x:0:0:0:0:0:0:182 through : 184), as well as the ip destination address for the peer delay mechanism (ff02:0:0:0:0: 0:0:6b) may be enabled via the 1588 port tx parsing configuration register (1588_tx_parse_config) . these ip addresses map to the 802.3 mac addresses of 33:33:00:00:01:81 through 33:33:00:00:01: 84 and 33:33:00:00:00:6b. any of these addr esses are allowed for peer delay and non- peer delay messages. a user defined mac address defined in the 1588 user mac address high-word register (1588_us- er_mac_hi) and the 1588 user mac address low-dwo rd register (1588_user_mac_lo) may also be indi- vidually enabled for the above formats. if the type / length field indicates an ethertype then for the layer 2 message format, the ethertype must equal 0x88f7. for ipv4/udp messages, the ethertype must equal 0x0800. for ipv6/udp messages, the ethertype must equal 0x86dd. if the type / length field indicates a length and the next 3 bytes equal 0xaaaa03 (indicating that a snap header is present) and the snap header has a oui equal to 0x000000 then for the layer 2 message format, the ethertype in the snap header must equal 0x88f7. for ipv4/udp messages, the ethertype in the snap header must equal 0x0800. for ipv6/udp messages, the ethertype in the snap header must equal 0x86dd. for ipv4/udp messages, the version field in the ipv4 header must equal 4, the ihl field must be 5 and the proto- col field must equal 17 (udp) or 51 (ah). ipv4 options are not supported. for ipv6/udp messages, the version field in the ipv6 hea der must equal 6 and the next header field must equal 17 (udp) or one of the ipv6 extension header values (0 - hop-by-hop options, 60 - destination options, 43 - routing, 44 - fragment, 51 - authentication header (ah) for ipv4/udp messages, destination ip address checking is enabled via the tx ip address enable (tx_ip_ad- dr_en) in the 1588 port tx parsing configuratio n register (1588_tx_parse_config) . any of the iana assigned multicast ip destination addresses for ieee 1588 ( 224.0.1.129 and 224.0.1.130 through .132), as well as the ip destination address for the peer dela y mechanism (224.0.0.107) may be enabled via the 1588 port tx parsing configuration register (1588_tx_parse_config) . any of these addresses are allowed for peer delay and non-peer delay messages. for ipv6/udp messages, destination ip address checking is enabled via the tx ip address enable (tx_ip_ad- dr_en) in the 1588 port tx parsing configuratio n register (1588_tx_parse_config) . any of the iana assigned multicast ip destination addresses for ieee 1588 (ff0x:0:0:0:0:0:0:181 and ff0x:0:0:0:0:0:0:182 through :184), as well as the ip destination address for the peer delay mechanism (f f02:0:0:0:0:0:0:6b) may be enabled via the 1588 port tx parsing configurat ion register (1588_tx_parse_config) . any of these downloaded from: http:///
lan9250 ds00001913a-page 308 ? 2015 microchip technology inc. addresses are allowed for peer delay and non-peer delay messages. for ipv4/udp if the protocol field in the fixed header wa s 51 (ah), the next header field is checked for 17 (udp) and the ah header is skipped. for ipv6/udp if the next header field in the fixed hea der was one of the ipv6 extens ion header values, the next header field in the extension header is checked for 17 (udp) or one of the ipv6 extension header values. if it is one of the ipv6 extension header values, the process repeats until either a value of 17 (udp) or a value of 59 (no next header) are found or the packet ends. 14.2.2.3 transmit messa ge egress time recording following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked for all of the following. the messagetype field of the ptp header is c hecked and only those messages enabled via the tx ptp message type enable (tx_pt p_message_en[15:0]) bits in the 1588 port tx timestamp configuration register (1588_tx_timestamp_config) will be have their egress times saved. typically sync, delay_req, pde- lay_req and pdelay_resp messages are enabled. the versionptp field of the pt p header is checked against the tx ptp version (tx_ptp_version[3:0]) field in the 1588 port tx timestamp configuration register (1588_tx_timestamp_config) . only those messages with a matching version will be have their egress time s saved. a setting of 0 allows any ptp version. note: support for the ieee 1588-2002 (v1) packet format is not provided. if enabled via the tx ptp domain match enable (tx_ptp_domain_en) bit in the 1588 port tx timestamp configuration register (1588_tx_timestamp_config) , the domainnumber field of the ptp header is checked against the tx ptp domain (t x_ptp_domain[7:0]) value in the same register. only those messages with a matching domain will be have their egress times saved. if enabled via the tx ptp alternate master e nable (tx_ptp_ alt_master_en) bit in the 1588 port tx time- stamp configuration register (1588_tx_timestamp_config) , the alternatemasterflag in the flagfield of the ptp header is checked and only those messages with an alternatemasterflag set to 0 will be have their egress times saved. at the end of the frame, the frames fc s and the udp checksum (for ipv4 and ipv6 formats) are verified. fcs checking can be disabled using the tx ptp fcs check disab le (tx_ptp_fcs_dis) bit in the 1588 port tx timestamp config- uration register (158 8_tx_timestamp_config) . udp checksum checking can be disabled using the tx ptp udp checksum check disable (tx_ptp_udp_chksum_dis) bit in the same register. note: a ipv4 udp checksum value of 0x00 00 indicates that the checksum is not included and is considered a pass. a ipv6 udp checksum value of 0x0000 is invalid and is considered a fail. note: for ipv6, the udp checksum calculatio n includes the ipv6 pseudo heade r. part of the ipv6 pseudo header is the final ipv6 destination address. if the ipv6 packet does not contain a routing header, t hen the final ipv6 destination address is the destina- tion address contained in the ipv6 header. if the ipv6 packet does contain a routing header, then the final ipv6 destination address is the address in the last element of the routing header. note: the udp checksum is calculated over the entire udp payload as indicat ed by the udp length field and not the assumed ptp packet length. note: the udp checksum calculation does not included layer 2 pad bytes, if any. if the fcs and checksum tests pass: the latency adjusted, 1588 clock value, saved above at the start of the frame, is recorded into the 1588 port tx egress time seconds register (1588_tx_egress_sec) and 1588 port tx egress time nanoseconds regis- ter (1588_tx_egress_ns) . the messagetype and sequenceid fields and 12-bit crc of the portidentity field of the ptp header are recorded into the message type (msg_type) , sequence id (seq_id) and source port identity crc (src_prt_crc) fields of the 1588 port tx message header register (1588_tx_msg_header) . the 12-bit crc of the portidentity field is created by using the polynomial of x 12 + x 11 + x 3 + x 2 + x + 1. the corresponding maskable 1588 tx timestamp interrupt (1588_tx_ts_int) is set in the 1588 interrupt status register (1588_int_sts) . downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 309 lan9250 up to four transmit events are saved per port with the count shown in the 1588 tx timestamp count (1588_tx- _ts_cnt[2:0]) field in the 1588 port capture information register (1588_cap_info) . additional events are not recorded. when the appropriate 1588 tx timestamp interrupt (1588_tx_ts_int) bit is written as a one to clear, 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) will decrement. if there are remainin g events, the capture registers will update to the next event and the interrupt will set again. delay_req egress time saving normally, in ordinary clock operation, the egress time of transmitted delay_req packets are saved and read by the host s/w. to avoid the need to read these timestamps via register access, the egress time of the last transmitted delay_req packet on the port can be inserted into delay_resp packets received on the port. the 1588 port tx delay_req egress time seconds register (1588_tx_dreq_sec) and the 1588 port tx delay_req egress time nanoseconds register (1588_tx_dreq_ns) hold the egress time of the delay_req mes- sage. these registers are updated by the h/w when the delay_req message is transmitted independent of the settings in the tx ptp message type enable (tx_ptp_message_en[15:0]) bits. as above (including all applicable notes): the versionptp and domainnumber fields and alternat emasterflag in the flagfield of the ptp header are checked, if enabled. note: support for the ieee 1588 -2002 (v1) packet format is not provided. at the end of the frame, the frames fcs and the udp ch ecksum (for ipv4 and ipv6 formats) are verified, if enabled. if all tests pass, then the delay_req message information is updated and available for the receive function. 14.2.2.4 egress packet modifications egress time insertion - sync message function while functioning as an ordinary clock master, one-step tran smission of sync messages from the host s/w requires the actual egress time to be inserted into the ten byte, origin timestamp field. the 32-bit nanoseconds portion and the lower 32 bits of the seconds portion come from the latency adjust ed, 1588 clock value, saved above at the start of the frame. the upper 16 bits of seconds are taken from the 1588 tx one-step sync upper se conds register (1588_tx_one_- step_sync_sec) . the host software is responsible for maintaining this register if required. note: inserting the egress time into the packet is an additional, separately enabled, feature verses the egress time recording described above. this function is enabled via the tx ptp sync message egress time insertion (tx_ptp_sync_ts_insert) bit in the 1588 port tx modification register (1588_tx_mod) and is used only on frames which have bit 7 of the ptp headers reserved byte cleared. note: the offset of the reserved byte is specified by the tx ptp 1 reserved byte offset (tx_pt p_1_rsvd_off- set[5:0]) field in the 1588 port tx modification register (1588_tx_mod) . proper operation of the transmitter re quires that the reserved byte resides after the versionptp field and before the correctionfield. for version 2 of ieee 1588, the reserved byte at offset 5 should be used. following the determination of packet fo rmat and qualification of the packet as a ptp message above, the ptp header is checked. the versionptp field of the pt p header is checked against the tx ptp version (tx_ptp_version[3:0]) field in the 1588 port tx timestamp configuration register (1588_tx_timestamp_config) . only those messages with a matching version will have their egress time in serted. a setting of 0 allows any ptp version. note: the domainnumber field and alternatemasterflag in the flagfield of the ptp header are not tested. note: support for the ieee 1588 -2002 (v1) packet format is not provided. egress correction field turnaround time adjustment - pdelay_resp message function one-step pdelay_resp messages sent by t he host, require their correctionfield to be calculated on-the-fly to include the turnaround time between the ingress of the p delay_req and the egress time of the pdelay_resp. pdelay_resp.cf = pdelay_req.cf + pdelay_resp.egress time - pdelay_req.ingress time. downloaded from: http:///
lan9250 ds00001913a-page 310 ? 2015 microchip technology inc. note: adjusting the correction field in the packet is an additional, separately enabled, feature verses the egress time recording described above. note: if the original correctionfield contains a va lue of 7fffffffffffffff, it is not modified. if adjustment to the correctionfield would result in a value that is larger than 7fffffffffffffff, that value is used instead. the 1588 port rx pdelay_req ingress time seconds register (1588_rx_pdreq_sec) and the 1588 port rx pde- lay_req ingress time nanoseconds register (1588_rx_pdreq_ns) hold the ingress time of the pdelay_req mes- sage. the 1588 port rx pdelay_req ingress correctio n field high register (1588_rx_pdreq_cf_hi) and the 1588 port rx pdelay_req ingress correction field low register (1588_rx_pdreq_cf_low) hold the correctionfield of the pdelay_req message. these registers are set by s/w prior to sending the pd elay_resp message or by th e automatic updating described above in pdelay_req ingress time saving . the egress time is the latency adjusted, 1588 clock valu e, saved above at the start of the pdelay_resp frame. note: since only four bits worth of seconds of the pdelay_r eq ingress time are stored, the host must send the pdelay_resp within 16 seconds. this function is enabled via the tx ptp pdelay_resp message turnaround time insertion (tx_ptp_pdre- sp_ta_insert) bit in the 1588 port tx modification register (1588_tx_mod) and is used only on frames which have bit 7 of the ptp headers reserved byte cleared. as with egress time insertion above: the versionptp field of the ptp header is checked a nd the domainnumber field and alternatemasterflag in the flagfield of the ptp header are not checked note: support for the ieee 1588 -2002 (v1) packet format is not provided. frame updating frames are modified even if their original fcs or udp checksum is invalid. for ipv4, the udp checksum is set to 0 under the following conditions. if the tx ptp clear udp/ipv4 checksum enable (tx_ptp_cl r_udpv4_chksum) bit in the 1588 port tx modification register 2 (1588_tx_mod2) is set and either sync egress time insertion or pdelay_resp correc- tion field turnaround time adjustment is enabled, the udp checksum is set to 0 for all ptp messages. the actual message type and the pt p_version field are not checked. for ipv6, the two bytes beyond the end of the ptp message are modified to correct for the udp checksum. these bytes are updated by accumulating the differences between the original frame data and the substituted data using the mechanism defined in ietf rfc 1624. it is assumed that the existing two bytes are zero and are replaced. it is assumed that the original udp checksum is valid and is not checked. note: since the two bytes beyond the end of the ptp message are modified based on the differences between the original frame data and the substituted data, an in valid incoming checksum wo uld result in an outgoing checksum error. note: the two bytes beyond the end of the ptp message are located by using the messagelength field from the ptp header. the frame fcs is recomputed it is assumed that the original fcs is valid and is not checked. if the frame has a transmit symbol error(s), a transmit sym bol error indication will be propagated at the same nib- ble location(s) note: the fcs and ipv6/udp checksum are updated only if the frame was actually modified. the ipv4/udp checksum is cleared as indicated above and could be the only modification in the message. if the ipv4/udp checksum is cl eared, the fcs is recomputed. if no modifications are done, the existi ng fcs and checksums are left unchanged. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 311 lan9250 14.3 1588 clock the tunable 1588 clock is the time source for all ptp related functions of the device. the block diagram is shown in figure 14-1 . the 1588 clock consists of a 32-bit wide seconds portion and a 30-bit wide nanoseconds portion. running at a nominal reference frequency of 100mhz, the nanoseconds portion is normally incremented by a value of 10 every reference clock period. upon reaching or exceeding its maximum value of 10^9, the nanoseconds portion rolls over to or past zero and the seconds portion is incremented. the 1588 clock can be read by setting the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) . this saves the current value of the 1588 clock into the 1588 clock seconds register (1588_clock_sec) , 1588 clock nanoseconds register (1588_clock_ns) and 1588 clock sub-nanoseconds register (1588_clock_subns) where it can be read. although the ieee 1588-2008 specification calls for a 48-bit se conds counter, the hardware only supports 32 bits. for purposes of event timestamping, residence time correction or other comparisons, the 136 year rollover time of 32 bits is sufficient. rollover can be detected and corrected by compar ing the two values of interest. to support one-step oper- ations, the device can insert the egress timestamp into th e origin timestamp field of sync messages. however, the host must maintain the 1588 tx one-step sync upper seconds register (1588_tx_one_step_sync_sec) . the host should avoid sending a sync message if there is a possibility t hat the 32-bit seconds counter will reach its rollover value before the message is transmitted. a 32-bit sub-nanoseconds counter is used to precisely tune t he rate of the 1588 clock by accounting for the difference between the nominal 10ns and the actual rate of the master clock. every re ference clock period the sub-nanoseconds counter is incremented by the clock rate adjustment value (1588_clock_rate_adj_value) in the 1588 clock rate adjustment register (1588_clock_rate_adj) , specified in 2 -32 nanoseconds. when the sub-nanoseconds counter rolls over past zero, the nanoseconds portion of th e 1588 clock is incremented by 9 or 11 instead of the normal value of 10. the choice to speed up or slow down is determined by the clock rate adjustment direction (1588_clock_rate_adj_dir) bit. the ability to adjust for 1 ns approximately every 43 seconds allows for a tuning precision of approximately 2.3 -9 percent. the maximum adjustment is 1 n s every 4 clocks (40 ns) or 2.5 percent. figure 14-1: 1588 clock block diagram ieee 1588 clock carry 32 bit seconds + 9, 10, 11 inc 30 bit nanoseconds 32 bit subnanoseconds + 30 bit rate adjustment carry + / - + step value host 30 bit temp rate adjustment 32 bit temp rate duration downloaded from: http:///
lan9250 ds00001913a-page 312 ? 2015 microchip technology inc. in addition to adjusting the frequency of the 1588 clock, the host may directly set the 1588 clock, make a one-time step adjustment of the 1588 clock or specify a temporary rate. the choice of method depends on needed adjustment. for initial adjustments, direct or one-ti me step adjustments may be best. for on- going minor adjustments, the temporary rate adjustment may be best. ideally, the frequency will be matc hed and once the 1588 clock is synchronized, no further adjustments would be needed. in order to perform a direct writing of the 1588 clock, the desired value is written into the 1588 clock seconds register (1588_clock_sec) , 1588 clock nanoseconds register (1588_clock_ns) and 1588 clock sub-nanoseconds register (1588_clock_subns) . the clock load (1588_clock_load) bit in the 1588 command and control reg- ister (1588_cmd_ctl) is then set. in order to perform a one-time positive or negative adjus tment to the seconds portion of the 1588 clock, the desired change and direction are written into the 1588 clock step adjustment register (1588_clock_step_adj) . the clock step seconds (1588_clock_step_seconds) bit in the 1588 command and control register (1588_cmd_ctl) is then set. the internal sub-nanoseconds counter and the nanoseconds portion of the 1588 cl ock are not affected. if a nanoseconds portion rollover coincides with the 1588 clock adjustment, the 1588 clock adjustment is applied in addi- tion to the seconds increment. in order to perform a one-time positiv e adjustment to the nanoseconds portion of the 1588 clock, the desired change is written into the 1588 clock step adjustment r egister (1588_clock_step_adj) . the clock step nanoseconds (1588_clock_step_nanoseconds) bit in the 1588 command and control register (1588_cmd_ctl) is then set. if the addition to the nanoseconds portion results in a rollover past zero, then the seconds portion of the 1588 clock is incremented. the normal (9, 10 or 11 ns) increment to th e nanoseconds portion is suppressed for one clock. this can be compensated for by specifying an addition value 10ns higher. a side benefit is that using an addition value of 0 effec- tively pauses the 1588 clock for 10ns while a value less than 10 slows the clock down just briefly. the internal sub- nanoseconds counter of the 1588 clock is not affected by the adjustment, however, if a sub-nanoseconds counter roll- over coincides with the 1588 clock adjustment it will be missed. in order to perform a temporary rate adjus tment of the 1588 clock, the desired temporary rate and direction are written into the 1588 clock temporary rate adjustment register (1588_clock_temp_rate_adj) and the duration of the temporary rate, specified in referenc e clock cycles, is written into the 1588 clock temporary rate duration register (1588_clock_temp_rate_duration) . the clock temporary rate (1588_clock_temp_rate) bit in the 1588 command and control register (1588_cmd_ctl) is then set. once the temporar y rate duration expires, the clock temporary rate (1588_clock_temp_rate) bit will self-clear and the 1588 clock rate adjustment register (1588_clock_rate_adj) will once again control the 1588 clock rate. this method of adjusting the 1588 clock may be preferred since it avoids large disc rete changes in the 1588 clock value. for a maximum setting in both the 1588 clock temporary rate adjustment register (1588_clock_temp_rate_adj) and 1588 clock temporary rate dura- tion register (1588_clock_temp_rate_duration) , the 1588 clock can be adjusted by approximately 1 second. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 313 lan9250 14.4 1588 clock events the 1588 clock events block is responsible for generating and controlling all 1588 clock related events. two clock event channels, a and b, are availabl e. the block diagram is shown in figure 14-2 . for each clock event channel, a comparator compar es the 1588 clock with a clock target loaded in the 1588 clock target x seconds register (1588_clock_target_sec_x) and 1588 clock target x nanoseconds register (1588_clock_target_ns_x) . the clock target register pair requires two 32-bit write cycles, one to each half, befo re the register pair is affected. the writes may be in any order. there is a register pair for each clock event channel (a and b). the clock target can be read by setting the clock target read (1588_clock_target_read) bit in the 1588 com- mand and control register (1588_cmd_ctl) . this saves the current value of the both clock targets (a and b) into the 1588 clock target x seconds register (1588_clock_target_sec_x) and 1588 clock target x nanoseconds reg- ister (1588_clock_target_ns_x) where they can be read. when the 1588 clock reaches or passes the clock target for a clock event channel, a clock event occurs which triggers the following: the maskable interrupt for that clock event channel ( 1588 timer interrupt a (1588_timer_int_a) or 1588 timer interrupt b (1588_timer_int_b) ) is set in the 1588 interrupt status register (1588_int_sts) . the reload/add a (reload_add_a) or reload/add b (reload_add_b) bit in the 1588 general configuration register (1588_general_config) is checked to determine the new clock target behavior: Creload_add = 1: the new clock target is loaded from the reload / add registers ( 1588 clock target x reload / add seconds register (1588_clock_target_reload_sec_x) and 1588 clock target x reload / add nanoseconds register (1588_clock_target_reload_ns_x) ). Creload_add = 0: the clock target is incremented by the reload / add registers ( 1588 clock target x reload / add seconds register (1588_clock_target_reload_sec_x) and 1588 clock target x reload / add nanoseconds register (1588_clock_target_reload_ns_x) ). the clock target nanoseconds rolls over at 10^9 and the carry is added to the clock target seconds. the clock target reload / add register pair requires two 32-bit write cycles, one to each half, before the register pair is affected. the writes may be in any order. there is a register pair for each clock event channel (a and b). note: writing the 1588 clock may cause the interrupt event to occur if the new 1588 clock value is set equal to or greater than the current clock target. the clock target reload function (reload_add = 1) allows the host to pre-load the next trigger time in advance. the add function (reload_add = 0), allows for a automatic repeatable event. figure 14-2: 1588 clock event block diagram ieee 1588 clock events compare >= load / add host 1588 clock reload / add a or b clock target a or b irq flag a or b gpio events gpio clears downloaded from: http:///
lan9250 ds00001913a-page 314 ? 2015 microchip technology inc. 14.5 1588 gpios in addition to time stamping ptp packets, the 1588 clock val ue can be saved into a set of clock capture registers based on the gpio inputs. the gpio inputs can also be used to clear the 1588 clock target compare event interrupt. when configured as outputs, gpios can be used to output a signal based on an 1588 clock target compare events. note: the ieee 1588 unit supports up to 3 gpio signals. 14.5.1 1588 gpio inputs 14.5.1.1 gpio even t clock capture when the gpio pins are configur ed as inputs, and enabled with the gpio rising edge capture enable 2-0 (gpio_re_- capture_enable[2:0]) or gpio falling edge capture enable 2-0 (gpio_fe_capture_enable[2:0]) bits in the 1588 gpio capture conf iguration register (1588_gpio_cap_config) , a rising or falling edge, respectively, will cap- ture the 1588 clock into the 1588 gpio x rising edge clock seconds capture register (1588_gpio_re_- clock_sec_cap_x) and the 1588 gpio x rising edge clock nanoseconds capture register (1588_gpio_re_clock_ns_cap_x) or 1588 gpio x falling edge clock sec onds capture register (1588_gpi- o_fe_clock_sec_cap_x) and the 1588 gpio x falling edge clock nanoseconds capture register (1588_gpi- o_fe_clock_ns_cap_x) where x equals the number of the active gpio input. gpio inputs must be stable for greater than 40 ns to be recognized as capture events and are edge sensitive. the gpio inputs have a fixed capture latency of 65 ns that can be accounted for by the host driver. the gpio inputs have a capture latency uncertainty of +/-5 ns. the corresponding, mask able, interrupt flags 1588 gpio rising edge interrupt (1588_gpio_re_int[7:0]) or 1588 gpio falling edge interrupt (1588_gpio_fe_int[7:0]) in the 1588 interrupt status register (1588_int_sts) will also be set. this is in addition to the interrupts available in the general purpose i/o interrupt status and enable register (gpio_int_sts_en) . a lock enable bit is provided for each timestamp enabled gpio, lock enable gpio rising edge (lock_gpio_re) and lock enable gpio falli ng edge (lock_gpio_fe) in the 1588 gpio capture configurat ion register (1588_gpio_- cap_config) , which prevents the corresponding gpio clock captur e registers from being overwritten if the gpio interrupt in 1588 interrupt status register (1588_int_sts) is already set. 14.5.1.2 gpio timer interrupt clear the gpio inputs can also be configured to clear the 1588 timer interrupt a (1588_timer_int_a) or 1588 timer inter- rupt b (1588_timer_int_b) in the 1588 interrupt status register (1588_int_sts) by setting the corresponding enable and select bits in the 1588 general configuration register (1588_general_config) . the polarity of the gpio input is determined by the gpio interrupt/1588 polari ty 2-0 (gpio_pol[2:0]) bits in the gen- eral purpose i/o configur ation register (gpio_cfg) . gpio inputs must be active for greater than 40 ns to be recognized as interrupt clear events and are edge sensitive. 14.5.2 1588 gpio outputs upon detection of a clock target a or b compare event, the corresponding clock event channel can be configured to output a 100 ns pulse, toggle its output, or reflect its 1588 timer interrupt bit. the selection is made using the clock event channel a mode (clock_event_a) and clock event channel b mode (clock_event_b) bits of the 1588 general configuration register (1588_general_config) . a gpio pin is configured as a 1588 ev ent output by setting the corresponding 1588 gpio output enable 2-0 (1588_g- pio_oe[2:0]) bits in the general purpose i/o configur ation register (gpio_cfg) . these bits override the gpio direc- tion bits of the general purpose i/o data & direction register (gpio_data_dir) and allow for gpio output generation based on the 1588 clock target compare event. the c hoice of the event channel is controlled by the 1588 gpio chan- nel select 2-0 (gpio_ch_sel[2:0]) bits in the general purpose i/o configuration register (gpio_cfg) . note: the 1588 gpio output enable 2-0 (1588_gpio_oe[2:0]) bits do not override the gpio buffer type 2-0 (gpiobuf[2:0]) in the general purpose i/o configuration register (gpio_cfg) . the clock event polarity, which determines whether the 1588 gpio output is active high or active low, is controlled by the gpio interrupt/1588 polarity 2-0 (gpio_pol[2:0]) bits in the general purpose i/o configuration register (gpi- o_cfg) . the gpio outputs have a latency of approximately 40 ns wh en using 100 ns pulse or i nterrupt bit modes and 30 ns when using toggle mode. on chip delays contribu te an uncertainty of +/-4ns to these values. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 315 lan9250 14.6 software triggered clock capture as an alternative, the gpio capture r egisters can be used by host software to recorded software events by specifying the gpio register set in the 1588 manual capture select 3-0 (1588_manual_capture_sel[3:0]) and setting the 1588 manual capture (1588_manual_capture) bit in the 1588 command and control register (1588_cmd_ctl) . this also causes the corresponding bit in the 1588 interrupt status register (1588_int_sts) to set. note: the interrupts available in the general purpose i/o interrupt status and enable register (gpi- o_int_sts_en) are not set by the using this method. note: the lock enable gpio rising edge (lock_gpio_re) and lock enable gpio falling edge (lock_gpi- o_fe) bits do not apply to manual clock capture. the full set of gpio capture registers is always available regardless of the number of gpios supported by the device. 14.7 1588 interrupt the ieee 1588 unit provid es multiple interrupt conditions. these includ e timestamp indi cation on the tr ansmitter and receiver, individual gpio input timestamp interrupts, and a clock comparison event interrupts. all 1588 interrupts are located in the 1588 interrupt status register (1588_int_sts) and are fully maskable via their respective enable bits in the 1588 interrupt enable register (1588_int_en) . all 1588 interrupts are anded with their indi vidual enables and then ored, generating the 1588 interrupt event (1588_evnt) bit of the interrupt status register (int_sts) . when configured as inputs, the gpios have the added functionality of clearing the 1588 timer interrupt a (1588_tim- er_int_a) or 1588 timer interrupt b (1588_timer_int_b) bits of the 1588 interrupt status register (1588_int_sts) as described in section 14.5.1.2 . refer to section 8.0, "system interrupts," on page 62 for additional information on the device interrupts. downloaded from: http:///
lan9250 ds00001913a-page 316 ? 2015 microchip technology inc. 14.8 1588 registers this section details the directly addr essable ptp timestamp related registers. for gpio related registers, the wildcard x should be replaced with 0 through 7. similarly, for clock compare events, the wildcard x should be replaced with a or b. port and gpio registers share a comm on address space. port vs. gpio re gisters are selected by using the bank select (bank_sel[2:0] in the 1588 bank port gpio select register (1588_bank_port_gpio_sel) . the gpio accessed (x) is set by the gpio select (gpio_sel[2:0]) field. note: the ieee 1588 unit supports 3 gpio signals. for an overview of the entire directly addressable register map, refer to section 5.0, "register map," on page 29 . table 14-1: 1588 control and status registers bank select address offset register name (symbol) na 100h 1588 command and control register (1588_cmd_ctl) na 104h 1588 general configuration register (1588_general_config) na 108h 1588 interrupt status register (1588_int_sts) na 10ch 1588 interrupt enable register (1588_int_en) na 110h 1588 clock seconds register (1588_clock_sec) na 114h 1588 clock nanoseconds register (1588_clock_ns) na 118h 1588 clock sub-nanoseconds register (1588_clock_subns) na 11ch 1588 clock rate adjustment register (1588_clock_rate_adj) na 120h 1588 clock temporary rate adjustm ent register (1588_clock_temp_rate_- adj) na 124h 1588 clock temporary rate duration register (1588_clock_temp_rate_du- ration) na 128h 1588 clock step adjustment register (1588_clock_step_adj) na 12ch 1588 clock target x seconds register (1588_clock_target_sec_x) x=a na 130h 1588 clock target x nanoseconds register (1588_clock_target_ns_x) x=a na 134h 1588 clock target x reload / add seconds register (1588_clock_target_re- load_sec_x) x=a na 138h 1588 clock target x reload / add n anoseconds register (1588_clock_tar- get_reload_ns_x) x=a na 13ch 1588 clock target x seconds register (1588_clock_target_sec_x) x=b na 140h 1588 clock target x nanoseconds register (1588_clock_target_ns_x) x=b na 144h 1588 clock target x reload / add seconds register (1588_clock_target_re- load_sec_x) x=b na 148h 1588 clock target x reload / add n anoseconds register (1588_clock_tar- get_reload_ns_x) x=b na 14ch 1588 user mac address high-word register (1588_user_mac_hi) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 317 lan9250 na 150h 1588 user mac address low-dword register (1588_user_mac_lo) na 154h 1588 bank port gpio select register (1588_bank_port_gpio_sel) 0 158h 1588 port latency register (1588_latency) 0 15ch 1588 port asymmetry and peer delay register (1588_asym_peerdly) 0 160h 1588 port capture information register (1588_cap_info) 1 158h 1588 port rx parsing configuratio n register (1588_rx_parse_config) 1 15ch 1588 port rx timestamp configurat ion register (1588_rx_timestamp_con- fig) 1 160h 1588 port rx timestamp insertion conf iguration register (1588_rx_ts_insert_- config) 1 168h 1588 port rx filter configuratio n register (1588_rx_filter_config) 1 16ch 1588 port rx ingress time seconds register (1588_rx_ingress_sec) 1 170h 1588 port rx ingress time nanoseconds register (1588_rx_ingress_ns) 1 174h 1588 port rx message header register (1588_rx_msg_header) 1 178h 1588 port rx pdelay_req ingress time seconds register (1588_rx_p- dreq_sec) 1 17ch 1588 port rx pdelay_req ingress time nanoseconds register (1588_rx_p- dreq_ns) 1 180h 1588 port rx pdelay_req ingress corre ction field high register (1588_rx_p- dreq_cf_hi) 1 184h 1588 port rx pdelay_req ingress correction field low register (1588_rx_p- dreq_cf_low) 1 188h 1588 port rx checksum dropped count register (1588_rx_chksum_- dropped_cnt) 1 18ch 1588 port rx filtered count register (1588_rx_filtered_cnt) 2 158h 1588 port tx parsing configuration register (1588_tx_parse_config) 2 15ch 1588 port tx timestamp configurat ion register (1588_tx_timestamp_config) 2 164h 1588 port tx modification register (1588_tx_mod) 2 168h 1588 port tx modification register 2 (1588_tx_mod2) 2 16ch 1588 port tx egress time seconds register (1588_tx_egress_sec) 2 170h 1588 port tx egress time nanoseconds register (1588_tx_egress_ns) 2 174h 1588 port tx message header register (1588_tx_msg_header) 2 178h 1588 port tx delay_req egress time seconds register (1588_tx_dreq_sec) 2 17ch 1588 port tx delay_req egress time nanoseconds register (1588_tx- _dreq_ns) table 14-1: 1588 control and status registers (continued) bank select address offset register name (symbol) downloaded from: http:///
lan9250 ds00001913a-page 318 ? 2015 microchip technology inc. 2 180h 1588 tx one-step sync upper seconds register (1588_tx_one_step_syn- c_sec) 3 15ch 1588 gpio capture configuratio n register (1588_gpio_cap_config) 3 16ch 1588 gpio x rising edge clock sec onds capture register (1588_gpio_re_- clock_sec_cap_x) 3 170h 1588 gpio x rising edge clock nanoseconds capture register (1588_gpi- o_re_clock_ns_cap_x) 3 178h 1588 gpio x falling edge clock seconds capture register (1588_gpio_fe_- clock_sec_cap_x) 3 17ch 1588 gpio x falling edge clock nanoseconds capture register (1588_gpi- o_fe_clock_ns_cap_x) table 14-1: 1588 control and status registers (continued) bank select address offset register name (symbol) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 319 lan9250 14.8.1 1588 command and cont rol register (1588_cmd_ctl) offset: 100h size: 32 bits bank: na bits description type default 31:14 reserved ro - 13 clock target read (1 588_clock_target_read) writing a one to this bit causes the current values of both of the 1588 clock targets (a and b) to be saved into the 1588 clock target x seconds register (1588_clock_target_sec_x) and the 1588 clock target x nanosec- onds register (1588_clock_target_ns_x) so they can be read. writing a zero to this bit has no affect. wo sc 0b 12:9 1588 manual capture select 3- 0 (1588_manual_capture_sel[3:0]) these bits specify which gpio 1588 clock capture registers are used during a manual capture. bit 3 selects the rising edge (0) or falling edge (1) registers. bits 2-0 select the gpio number. note: all 8 gpio register sets are available. r/w 0000b 8 1588 manual capture (1588_manual_capture) writing a one to this bit causes the current value of the 1588 clock to be saved into the gpio 1588 clock capture registers specified above. the corresponding bit in the 1588 interrupt status register (1588_int_sts) is also set. writing a zero to this bit has no affect. wo sc 0b 7 clock temporary rate (1588_clock_temp_rate) writing a one to this bit enables the use of the temporary clock rate adjust- ment specified in the 1588 clock temporary rate adjustment register (1588_clock_temp_rate_adj) for the duration specified in the 1588 clock temporary rate duration register (1588_clock_temp_rate_du- ration) . writing a zero to this bit has no affect. wo sc 0b 6 clock step nanoseconds (1588_clock_step_nanoseconds) writing a one to this bit adds the value of the clock step adjustment value (1588_clock_step_adj_value) field in the 1588 clock step adjustment register (1588_ clock_step_adj) to the nanoseconds portion of the 1588 clock. writing a zero to this bit has no affect. wo sc 0b downloaded from: http:///
lan9250 ds00001913a-page 320 ? 2015 microchip technology inc. note 1: the default value of this field is determined by the configuration strap 1588_enable_strap . 5 clock step seconds (1588_clock_step_seconds) writing a one to this bit adds or subtracts the value of the clock step adjust- ment value (1588_clock_step_adj_value) field in the 1588 clock step adjustment register (1588_clock_step_adj) to or from the seconds por- tion of the 1588 clock. the choice of adding or subtracting is set using the clock step adjustment directi on (1588_clock_step_adj_dir) bit. writing a zero to this bit has no affect. wo sc 0b 4 clock load (1588_clock_load) writing a one to this bit writes the value of the 1588 clock seconds register (1588_clock_sec) , the 1588 clock nanoseconds register (1588_clock_ns) and the 1588 clock sub-nanoseconds register (1588_clock_subns) into the 1588 clock. writing a zero to this bit has no affect. wo sc 0b 3 clock read (1588_clock_read) writing a one to this bit causes the current value of the 1588 clock to be saved into the 1588 clock seconds register (1588_clock_sec) , the 1588 clock nanoseconds register (1588_clock_ns) and the 1588 clock sub- nanoseconds register (1588_clock_subns) so it can be read. writing a zero to this bit has no affect. wo sc 0b 2 1588 enable (1588_enable) writing a one to this bit will enable the 1588 unit. reading this bit will return the current enabled value. writing a zero to this bit has no affect. r/w sc note 1: 1 1588 disable (1588_disable) writing a one to this bit will cause the 1588 enable (1588_enable) to clear once all current frame processing is completed. no new frame processing will be started if this bit is set. writing a zero to this bit has no affect. wo sc 0b 0 1588 reset (1588_reset) writing a one to this bit resets the 1588 h/w, state machines and registers and disables the 1588 unit. any frame modifications in progress are halted at the risk of causing frame data or fcs errors. 1588_reset should only be used once the 1588 unit is disabled as indicated by the 1588 enable (1588_enable) bit. note: writing a zero to this bit has no affect. wo sc 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 321 lan9250 14.8.2 1588 general configuration register (1588_general_config) offset: 104h size: 32 bits bank: na bits description type default 31:19 reserved ro - 18:17 reserved ro - 16 time-stamp unit en able (tsu_enable) this bit enables the receive and transmit functions of the time-stamp unit. the 1588 enable (1588_enable) bit in 1588 command and control regis- ter (1588_cmd_ctl) bit must also be set. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 15 gpio 1588 timer interru pt b clear enable (gpio_1588_timer_int_b_clear_en) this bit enables the selected gpio to clear the 1588_timer_int_b bit of the 1588 interrupt status register (1588_int_sts) . the gpio input is selected using the gpio 1588 timer interrupt b clear select (gpio_1588_timer_int_b_clear_sel[2:0]) bits in this register. the polarity of the gpio input is determined by gpio interrupt/1588 polarity 2-0 (gpio_pol[2:0]) in the general purpose i/o co nfiguration register (gpio_cfg) . note: the gpio must be configured as an input for this function to operate. for the clear function, gpio inputs are edge sensitive and must be active for greater than 40 ns to be recognized. r/w 0b 14:12 gpio 1588 timer interrupt b clear select (gpio_1588_timer_int_b_clear_sel[2:0]) these bits determine which gpio is used to clear the 1588 timer interrupt b (1588_timer_int_b) bit of the 1588 interrupt status register (1588_int_sts) . note: the ieee 1588 unit supp orts 3 gpio signals. r/w 000b downloaded from: http:///
lan9250 ds00001913a-page 322 ? 2015 microchip technology inc. 11 gpio 1588 timer interru pt a clear enable (gpio_1588_timer_int_a_clear_en) this bit enables the selected gpio to clear the 1588 timer interrupt a (1588_timer_int_a) bit of the 1588 interrupt status register (1588_int_sts) . the gpio input is selected using the gpio 1588 timer interrupt a clear select (gpio_1588_timer_int_a_clear_sel[2:0]) bits in this register. the polarity of the gpio input is determined by gpio interrupt/1588 polarity 2-0 (gpio_pol[2:0]) in the general purpose i/o configuration register (gpio_cfg) . note: the gpio must be configured as an input for this function to operate. for the clear function, gpio inputs are edge sensitive and must be active for greater than 40 ns to be recognized. r/w 0b 10:8 gpio 1588 timer interrupt a clear select (gpio_1588_timer_int_a_clear_sel[2:0]) these bits determine which gpio is used to clear the 1588_timer_int_a bit of the 1588 interrupt status r egister (1588_int_sts) . note: the ieee 1588 unit supp orts 3 gpio signals. r/w 000b 7:6 reserved ro - 5:4 clock event channel b mode (clock_event_b) these bits determine the output on clock event channel b when a clock tar- get compare event occurs. 00: 100ns pulse output 01: toggle output 10: 1588_timer_int_b bit value in 1588_int_sts_en register output 11: reserved note: the general purpose i/o configuration register (gpio_cfg) is used to enable the clock event onto the gpio pins as well as to set the polarity and output buffer type. r/w 00b 3:2 clock event channel a mode (clock_event_a) these bits determine the output on clock event channel a when a clock tar- get compare event occurs. 00: 100ns pulse output 01: toggle output 10: 1588_timer_int_a bit value in 1588_int_sts_en register output 11: reserved note: the general purpose i/o configuration register (gpio_cfg) is used to enable the clock event onto the gpio pins as well as to set the polarity and output buffer type. r/w 00b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 323 lan9250 1 reload/add b (reload_add_b) this bit determines the course of acti on when a clock target compare event for clock event channel b occurs. when set, the 1588 clock target x seconds register (1588_clock_tar- get_sec_x) and 1588 clock target x nanoseconds register (1588_clock_target_ns_x) are loaded from the 1588 clock target x reload / add seconds register (1588_clock_target_reload_sec_x) and 1588 clock target x reload / add nanoseconds register (1588_clock_target_reload_ns_x) x=b. when low, the clock target registers are incremented by the clock target reload registers. 0: increment upon a clock target compare event 1: reload upon a clock target compare event r/w 0b 0 reload/add a (reload_add_a) this bit determines the course of acti on when a clock target compare event for clock event channel a occurs. when set, the 1588 clock target x seconds register (1588_clock_tar- get_sec_x) and 1588 clock target x nanoseconds register (1588_clock_target_ns_x) are loaded from the 1588 clock target x reload / add seconds register (1588_clock_target_reload_sec_x) and 1588 clock target x reload / add nanoseconds register (1588_clock_target_reload_ns_x) x=a. when low, the clock target registers are incremented by the clock target reload registers. 0: increment upon a clock target compare event 1: reload upon a clock target compare event r/w 0b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 324 ? 2015 microchip technology inc. 14.8.3 1588 interrupt status register (1588_int_sts) this read/write register contains the 1588 interrupt status bits. writing a 1 to a interrupt status bits acknowledge s and clears the individual interrupt. if enabled in the 1588 interrupt enable register (1588_int_en) , these interrupt bits are cascaded into the 1588 interrupt event (1588_evnt) bit of the interrupt status register (int_sts) . status bits will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt. the 1588 interrupt event enable (1588_evnt_en) bit of the interrupt enable register (int_en) must also be set in order for an actual system level interrupt to occur. refer to section 8.0, "system interrupts," on page 62 for additional information. offset: 108h size: 32 bits bank: na bits description type default 31:24 1588 gpio falling edge interrupt (1588_gpio_fe_int[7:0]) this interrupt indicates that a falling event occurred and the 1588 clock was captured. note: as 1588 capture inputs, gpio inputs are edge sensitive and must be low for greater than 40 ns to be recognized as interrupt inputs. these bits can also be set due to a manual capture via 1588 manual capture (1588_manual_capture) . r/wc 00h 23:16 1588 gpio rising edge interru pt (1588_gpio_re_int[7:0]) this interrupt indicates that a rising event occurred and the 1588 clock was captured. note: as 1588 capture inputs, gpio inputs are edge sensitive and must be high for greater than 40 ns to be recognized as interrupt inputs. these bits can also be set due to a manual capture via 1588 manual capture (1588_manual_capture) . r/wc 00h 15:13 reserved ro - 12 1588 tx timestamp interrupt (1588_tx_ts_int) this interrupt indicates that a ptp pa cket was transmitted and its egress time stored. up to four events, as indicated by the 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) field in the 1588 port capture information register (1588_cap_info) , are buffered. r/wc 0b 11:9 reserved ro - 8 1588 rx timestamp interrupt (1588_rx_ts_int) this interrupt indicates that a ptp pa cket was received a nd its ingress time and associated data stored. up to four events, as indicated by the 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) field in the 1588 port capture information register (1588_cap_info) , are buffered. r/wc 0b 7:2 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 325 lan9250 1 1588 timer interrupt b (1588_timer_int_b) this interrupt indicates that the 1588 clock equaled or passed the clock event channel b clock target value in the 1588 clock target x seconds register (1588_cl ock_target_sec_x) and 1588 clock target x nano- seconds register (1588_clock_target_ns_x) x=b. note: this bit is also cleared by an active edge on a gpio if enabled. for the clear function, gpio input s are edge sensitive and must be active for greater than 40 ns to be recognized as a clear input. r/wc 0b 0 1588 timer interrupt a (1588_timer_int_a) this interrupt indicates that the 1588 clock equaled or passed the clock event channel a clock target value in the 1588 clock target x seconds register (1588_cl ock_target_sec_x) and 1588 clock target x nano- seconds register (1588_clock_target_ns_x) x=a. note: this bit is also cleared by an active edge on a gpio if enabled. for the clear function, gpio input s are edge sensitive and must be active for greater than 40 ns to be recognized as a clear input. r/wc 0b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 326 ? 2015 microchip technology inc. 14.8.4 1588 interrupt enable register (1588_int_en) this read/write register contains the 1588 interrupt enable bits. if enabled, these interrupt bits are cascaded into the 1588 interrupt event (1588_evnt) bit of the interrupt status reg- ister (int_sts) . writing a 1 to an interrupt enable bits will enable the corresponding interrupt as a source. status bits will still reflect the status of the interr upt source regardless of whether the source is enabled as an interrupt in this reg- ister. the 1588 interrupt event enable (1588_evnt_en) bit of the interrupt enable register (int_en) must also be set in order for an actual system leve l interrupt to occur. refer to section 8.0, "system interrupts," on page 62 for additional information. offset: 10ch size: 32 bits bank: na bits description type default 31:24 1588 gpio falling edge interrupt enable (1588_gpio_fe_en[7:0]) r/w 00h 23:16 1588 gpio rising edge interrupt enable (1588_gpio_re_en[7:0]) r/w 00h 15:13 reserved ro - 12 1588 tx timestamp enable (1588_tx_ts_en) r/w 0b 11:9 reserved ro - 8 1588 rx timestamp enable (1588_rx_ts_en) r/w 0b 7:2 reserved ro - 1 1588 timer b interrupt enable (1588_timer_en_b) r/w 0b 0 1588 timer a interrupt enable (1588_timer_en_a) r/w 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 327 lan9250 14.8.5 1588 clock seconds register (1588_clock_sec) this register contains the seconds po rtion of the 1588 clock. it is used to read the 1588 clock following the setting of the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) and to directly change the 1588 clock when the clock load (1588_clock_load) bit is set. note: the value read is the saved value of the 1588 clock when the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. offset: 110h size: 32 bits bank: na bits description type default 31:0 clock seconds (1588_clock_sec) this field contains the seconds portion of the 1588 clock. r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 328 ? 2015 microchip technology inc. 14.8.6 1588 clock nanoseconds register (1588_clock_ns) this register contains the nan oseconds portion of the 1588 clock. it is used to read the 1588 clock following the setting of the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) and to directly change the 1588 clock when the clock load (1588_clock_load) bit is set. note: the value read is the saved value of the 1588 clock when the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. offset: 114h size: 32 bits bank: na bits description type default 31:30 reserved ro - 29:0 clock nanoseconds (1588_clock_ns) this field contains the nanoseconds portion of the 1588 clock. r/w 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 329 lan9250 14.8.7 1588 clock sub-nanoseconds register (1588_clock_subns) this register contains the sub-nanoseconds portion of the 1588 clock. it is used to read the 1588 clock following the setting of the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) and to directly change the 1588 clock when the clock load (1588_clock_load) bit is set. note: the value read is the saved value of the 1588 clock when the clock read (1588_clock_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. offset: 118h size: 32 bits bank: na bits description type default 31:0 clock sub-nanoseconds (1588_clock_subns) this field contains the sub-nanoseconds portion of the 1588 clock. r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 330 ? 2015 microchip technology inc. 14.8.8 1588 clock rate adjustmen t register (1588 _clock_rate_adj) this register is used to adjust the rate of the 1588 clo ck. every 10 ns, 1588 clock is normally incremented by 10 ns. this register is used to occasionally change that increment to 9 or 11 ns. offset: 11ch size: 32 bits bank: na bits description type default 31 clock rate adjustment direction (1588_clock_rate_adj_dir) this field specifies if the 1588 rate ad justment causes the 1588 clock to be faster or slower than the reference clock. 0 = slower (1588 clock increments by 9 ns) 1 = faster (1588 clock increments by 11 ns) r/w 0b 30 reserved ro - 29:0 clock rate adjustment value (1588_clock_rate_adj_value) this field indicates an adjustment to the reference clock period of the 1588 clock in units of 2 -32 ns. on each 10 ns reference clock cycle, this value is added to the 32-bit sub-nanoseconds portion of the 1588 clock. when the sub-nanoseconds portion wraps around to zero, the 1588 clock will be adjusted by 1ns. r/w 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 331 lan9250 14.8.9 1588 clock temporary rate adjustment register (1588_clock_te mp_rate_adj) this register is used to temp orarily adjust the rate of the 1588 clock. ev ery 10 ns, 1588 clock is normally incremented by 10 ns. this register is used to occasio nally change that increment to 9 or 11 ns. offset: 120h size: 32 bits bank: na bits description type default 31 clock temporary rate adjustment direction (1588_clock_temp_rate_adj_dir) this field specifies if the 1588 tempor ary rate adjustment causes the 1588 clock to be faster or slower than the reference clock. 0 = slower (1588 clock increments by 9 ns) 1 = faster (1588 clock increments by 11 ns) r/w 0b 30 reserved ro - 29:0 clock temporary rate adjustment value (1588_clock_temp_rate_adj_value) this field indicates a temporary adjustment to the reference clock period of the 1588 clock in units of 2 -32 ns. on each 10ns reference clock cycle, this value is added to the 32-bit sub-nanoseconds portion of the 1588 clock. when the sub-nanoseconds portion wraps around to zero, the 1588 clock will be adjusted by 1ns (a 9 or 11 ns increment instead of the normal 10ns). r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 332 ? 2015 microchip technology inc. 14.8.10 1588 clock temporary rate duration register (1588_clock_temp_rate_duration) this register specifies the active duration of the temporary clock rate adjustment. offset: 124h size: 32 bits bank: na bits description type default 31:0 clock temporary rate duration (1588_clock_temp_rate_duration) this field specifies the dur ation of the temporary rate adjustment in reference clock cycles. r/w 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 333 lan9250 14.8.11 1588 clock step adjustment register (1588_clock_step_adj) this register is used to perform a one-time adjustment to ei ther the seconds portion or the nanoseconds portion of the 1588 clock. the amount and di rection can be specified. offset: 128h size: 32 bits bank: na bits description type default 31 clock step adjustment direction (1588_clock_step_adj_dir) this field specifies if the clock step adjustment value (1588_clock_- step_adj_value) is added to or subtracted from the 1588 clock. 0 = subtracted 1 = added note: only addition is supported for the nanoseconds portion of the 1588 clock r/w 0b 30 reserved ro - 29:0 clock step adjustment value (1588_clock_step_adj_value) when the nanoseconds portion of the 1 588 clock is being adjusted, this field specifies the amount to add. this is in lieu of the normal 9, 10 or 11 ns incre- ment. when the seconds portion of the 1588 clock is being adjusted, the lower 4 bits of this field specify the amount to add to or subtract. r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 334 ? 2015 microchip technology inc. 14.8.12 1588 clock target x seconds register (1588_clock_target_sec_x) this read/write regi ster combined with 1588 clock target x nanoseconds r egister (1588_clock_target_ns_x) form the 1588 clock target value. the 1588 clock target value is compared to the current 1588 clock value and can be used to trigger an interrupt upon at match. refer to section 14.4, "1588 clock events" for additional information. note: both this register and the 1588 clock target x nanoseconds r egister (1588_clock_target_ns_x) must be written for either to be affected. note: the value read is the saved value of the 1588 clock target when the clock target read (1588_clock_target_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. note: when the clock target read (1588_clock_target_read) bit is set, the previous value written to this register is overwritten. normally, a read command should not be requested in between writing this register and the 1588 clock target x nanoseconds register (1588_clock_target_ns_x) . offset: channel a: 12ch size: 32 bits channel b: 13ch bank: channel a: na channel b: na bits description type default 31:0 clock target seconds (clock_target_sec) this field contains the seconds portion of the 1588 clock compare value. r/w 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 335 lan9250 14.8.13 1588 clock target x nanoseconds register (1588_ clock_target_ns_x) this read/write register combined with 1588 clock target x seconds regi ster (1588_clock_target_sec_x) form the 1588 clock target value. the 1588 clock target value is compared to the current 1588 clock value and can be used to trigger an interrupt upon at match. refer to section 14.4, "1588 clock events" for additional information. note: both this register and the 1588 clock target x seconds register (1588_clock_target_sec_x) must be written for either to be affected. note: the value read is the saved value of the 1588 clock target when the clock target read (1588_clock_target_read) bit in the 1588 command and control register (1588_cmd_ctl) is set. note: when the clock target read (1588_clock_target_read) bit is set, the previous value written to this register is overwritten. normally, a read command should not be requested in between writing this register and the 1588 clock target x seconds register (1588_clock_target_sec_x) . offset: channel a: 130h size: 32 bits channel b: 140h bank: channel a: na channel b: na bits description type default 31:30 reserved ro - 29:0 clock target nanoseconds (clock_target_ns) this field contains the nanoseconds portion of the 1588 clock compare value. r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 336 ? 2015 microchip technology inc. 14.8.14 1588 clock target x re load / add seconds register (1588_clock_targ et_reload_sec_x) this read/write register combined with 1588 clock target x reload / add nanoseconds register (1588_clock_tar- get_reload_ns_x) form the 1588 clock target reload value. the 1588 clock target reload is the value that is reloaded or added to the 1588 clock compare value when a clock compare event occurs. refer to section 14.4, "1588 clock events" for additional information. note: both this register and the 1588 clock target x reload / add nanoseconds register (1588_clock_tar- get_reload_ns_x) must be written for either to be affected. offset: channel a: 134h size: 32 bits channel b: 144h bank: channel a: na channel b: na bits description type default 31:0 clock target reload seconds (clock_target_reload_sec) this field contains the seconds portion of the 1588 clock target reload value that is reloaded to the 1588 clock compare value. r/w 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 337 lan9250 14.8.15 1588 clock target x relo ad / add nanoseconds register (1588_clock_target_reload_ns_x) this read/write regi ster combined with 1588 clock target x reload / add seconds register (1588_clock_tar- get_reload_sec_x) form the 1588 clock target reload value. the 1588 clock target reload is the value that is reloaded or added to the 1588 clock compare value when a clock compare event occurs. refer to section 14.4, "1588 clock events" for additional information. note: both this register and the 1588 clock target x reload / add seconds register (1588_clock_tar- get_reload_sec_x) must be written for either to be affected. offset: channel a: 138h size: 32 bits channel b: 148h bank: channel a: na channel b: na bits description type default 31:30 reserved ro - 29:0 clock target reload nanoseconds (clock_target_reload_ns) this field contains the nanoseconds po rtion of the 1588 clock target reload value that is reloaded to the 1588 clock compare value. r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 338 ? 2015 microchip technology inc. 14.8.16 1588 user mac address high -word register (1588_user_mac_hi) this read/write regist er combined with the 1588 user mac address low-dword register (1588_user_mac_lo) forms the 48-bit user defined mac a ddress. the auxiliary mac address can be enabled for each protocol via their respective user defined mac address enable bit in the 1588 port rx parsing config uration register (1588_rx- _parse_config) . offset: 14ch size: 32 bits bank: na bits description type default 31:16 reserved ro - 15:0 user mac address high (user_mac_hi) this field contains the high 16 bits of the user defined mac address used for ptp packet detection. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 339 lan9250 14.8.17 1588 user mac address low-dw ord register (1 588_user_mac_lo) this read/write register combined with the 1588 user mac address high-word register (1588_user_mac_hi) forms the 48-bit user defined mac a ddress. the auxiliary mac address can be enabled for each protocol via their respective user defined mac address enable bit in the 1588 port rx parsing config uration register (1588_rx- _parse_config) . offset: 150h size: 32 bits bank: na bits description type default 31:0 user mac address low (user_mac_lo) this field contains the low 32 bits of the user defined mac address used for ptp packet detection. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 340 ? 2015 microchip technology inc. 14.8.18 1588 bank port gp io select register (15 88_bank_port_gpio_sel) offset: 154h size: 32 bits bank: na bits description type default 31:11 reserved ro - 10:8 gpio select (gpio_sel[2:0]) this field specifies which gpio the various gpio x registers will access. r/w 000b 7:3 reserved ro - 2:0 bank select (bank_sel[2:0] this field specifies which bank of registers is accessed. 000: port general 001: port rx 010: port tx 011: gpios 1xx: reserved r/w 000b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 341 lan9250 14.8.19 1588 port latency register (1588_latency) note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . note 2: the default value is appropriate for 100base-tx m ode. for other modes (100base-fx or 10base-t) the proper value needs to be set via software or eeprom. offset: 158h size: 32 bits bank: 0 bits description type default 31:16 tx latency (tx_latency[15:0]) this field specifies the egress delay in nanoseconds between the ptp time- stamp point and the network medium. the setting is used to adjust the inter- nally captured 1588 clock value such that the resultant timestamp more accurately corresponds to the start of the frames first symbol after the sfd on the network medium. the value depends on the port mode. typical values are: 100base-tx: 95ns 100base-fx: 68ns plus the receiv e latency of the fiber transceiver 10base-t: 1139ns note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 95 note 2 15:0 rx latency (rx_latency[15:0]) this field specifies the ingress delay in nanoseconds between the network medium and the ptp timestamp point. the setting is used to adjust the inter- nally captured 1588 clock value such t hat the resultant timestamp more accu- rately corresponds to the start of the frames first symbol after the sfd on the network medium. the value depends on the port mode. typical values are: 100base-tx: 285ns 100base-fx: 231ns plus the receiv e latency of the fiber transceiver 10base-t: 1674ns note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 285 note 2 downloaded from: http:///
lan9250 ds00001913a-page 342 ? 2015 microchip technology inc. 14.8.20 1588 port asymmetry and peer delay register (1588_asym_peerdly) note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 15ch size: 32 bits bank: 0 bits description type default 31:16 port delay asymmetry (delay_asym[15:0]) this field specifies the previously known delay asymmetry in nanoseconds. this is a signed 2s complement number. positive values occur when the master-to-slave or responder-to-reque stor propagation time is longer than the slave-to-master or requestor-t o-responder propagation time. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0000h 15:0 rx peer delay (r x_peer_delay[15:0]) this field specifies the measured pee r delay in nanoseconds used during peer-to-peer mode. r/w 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 343 lan9250 14.8.21 1588 port capture inform ation register (1588_cap_info) this read only register provides information about the receive and transmit capture buffers. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 160h size: 32 bits bank: 0 bits description type default 31:7 reserved ro - 6:4 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) this field indicates how many transmit ti mestamps are available to be read. it is incremented when a ptp packet is transmitted and decremented when the 1588 tx timestamp interrupt (1588_tx_ts_int) bit is written with a 1. ro 000b 3 reserved ro - 2:0 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) this field indicates how many receive timestamps are available to be read. it is incremented when a ptp packet is received and decremented when the 1588 rx timestamp interrupt (1588_rx_ts_int) bit is written with a 1. ro 000b downloaded from: http:///
lan9250 ds00001913a-page 344 ? 2015 microchip technology inc. 14.8.22 1588 port rx parsing configur ation register (1588_rx_parse_config) this register is used to configure the ptp receive message detection. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 158h size: 32 bits bank: 1 bits description type default 31:15 reserved ro - 14 rx layer 2 address 1 enable (rx_layer2_add1_en) this bit enables the layer 2 mac address of 01:80:c2:00:00:0e for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 13 rx layer 2 address 2 enable (rx_layer2_add2_en) this bit enables the layer 2 mac ad dress of 01:1b:19:00:00:00 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 12 rx address 1 enable (rx_add1_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:81 and ipv4 desti- nation address of 224.0.1.129 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:81 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:181 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 11 rx address 2 enable (rx_add2_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:82 and ipv4 desti- nation address of 224.0.1.130 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:82 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:182 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 345 lan9250 10 rx address 3 enable (rx_add3_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:83 and ipv4 desti- nation address of 224.0.1.131 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:83 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:183 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 9 rx address 4 enable (rx_add4_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:84 and ipv4 desti- nation address of 224.0.1.132 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:84 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:184 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 8 rx address 5 enable (rx_add5_en) this bit enables the ipv4 mac address of 01:00:5e:00:00:6b and ipv4 desti- nation address of 224.0.0.107 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:00:6b and ipv6 desti- nation address of ff02:0:0: 0:0:0:0:6b for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 7 rx user defined layer 2 mac address enable (rx_layer2_user_mac_en) this bit enables a user defined layer 2 mac address in ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 6 rx user defined ipv6 mac addr ess enable (rx_ipv6_user_mac_en) this bit enables a user defined ipv6 mac address in ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 5 rx user defined ipv4 mac addr ess enable (rx_ipv4_user_mac_en) this bit enables the user defined ipv4 mac address in ptp messages. the address is defined via the 1588 user mac address high-word register (1588_user_mac_hi) and the 1588 user mac address low-dword register (1588_user_mac_lo) . note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 346 ? 2015 microchip technology inc. 4 rx ip address enable (rx_ip_addr_en) this bit enables the checking of the ip destination address in ptp messages for both ipv4 and ipv6 formats. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 3 rx mac address enable (rx_mac_addr_en) this bit enables the checking of the mac destination address in ptp mes- sages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 2 rx layer 2 enable (rx_layer2_en) this bit enables the detection of the layer 2 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 1 rx ipv6 enable (rx_ipv6_en) this bit enables the detection of the udp/ipv6 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 0 rx ipv4 enable (rx_ipv4_en) this bit enables the detection of the udp/ipv4 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 347 lan9250 14.8.23 1588 port rx timest amp configuration register (1588_rx_timest amp_config) this register is used to configure ptp receive message timestamping. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 15ch size: 32 bits bank: 1 bits description type default 31:24 rx ptp domain (r x_ptp_domain[7:0]) this field specifies the ptp domain in use. if rx ptp domain match enable (rx_ptp_domain_en) is set, the domainnumber in the ptp message must matches the value in this field in order to recorded the ingress time. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 00h 23 rx ptp domain match en able (rx_ptp_domain_en) when this bit is set, the domainnumber in the ptp message is checked against the value in rx ptp domain (r x_ptp_domain[7:0]) . note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 22 rx ptp alternate master en able (rx_ptp_alt_master_en) when this bit is set, the alternatemas terflag in the ptp message is checked for a zero value. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 21 rx ptp udp checksum check di sable (rx_ptp_udp_chksum_dis) when this bit is cleared, ingress ti mes are not saved and ingress messages are not filtered if the frame has an in valid udp checksum. when this bit is set, the udp checksu m check is bypassed and the ingress time is saved and ingress messages are filtered regardless. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 20 rx ptp fcs check disab le (rx_ptp_fcs_dis) when this bit is cleared, ingress ti mes are not saved and ingress messages are not filtered if the fr ame has an invalid fcs. when this bit is set, the fcs check is bypassed. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b downloaded from: http:///
lan9250 ds00001913a-page 348 ? 2015 microchip technology inc. 19:16 rx ptp version (r x_ptp_version[3:0]) this field specifies the ptp version in use. a setting of 0 allows any ptp ver- sion. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 2h 15:0 rx ptp message type enable (rx_ptp_message_en[15:0]) these bits individually enable timestamping of their respective message types. bit 0 of this field corresponds to a message type value of 0 (sync), bit 1 to message type value 1 (delay_req), etc. typically sync, delay_req, pdelay _req and pdelay_resp messages are enabled. r/w 0000h bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 349 lan9250 14.8.24 1588 port rx timestamp in sertion configuration register (1588_rx_ts_insert_config) this register is used to configure ptp message timestamp insertion. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 160h size: 32 bits bank: 1 bits description type default 31:18 reserved ro - 17 rx ptp insert delay request egress in delay response enable (rx_ptp_insert_dreq_dresp_en) when this bit is set, the egress time of the last delay_req packet is inserted into received delay_resp packets. this bit has no affect if rx_ptp_inser t_ts_en is a low or if detection of the delay_resp message type is not enabled. r/w 0b 16 rx ptp bad udp checksu m force error disable (rx_ptp_bad_udp_chksum_force_err_dis) when this bit is cleared, ingress packets that have an invalid udp checksum will have a receive symbol error forced if the packet is modified for timestamp or correction field reasons. when this bit is set, the ud p checksum check is bypassed. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 15 rx ptp insert timestamp seconds enable (rx_ptp_insert_ts_sec_en) when rx_ptp_insert_ts_en is set, this bit enables bits 3:0 of the sec- onds portion of the receive ingress time to be inserted into the ptp message. this bit has no affect if rx_ptp_insert_ts_en is a low. r/w 0b 14 reserved ro - 13:8 rx ptp insert timestamp seconds offset (rx_ptp_insert_t s_sec_offset[5:0]) this field specifies the offset into the ptp header where the seconds portion of the receive ingress time is inserted. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 000101b 7 rx ptp insert timestamp en able (rx_ptp_insert_ts_en) when set, receive ingr ess times are inserted into the ptp message. r/w 0b 6 reserved ro - downloaded from: http:///
lan9250 ds00001913a-page 350 ? 2015 microchip technology inc. 5:0 rx ptp insert timestamp offset (rx_ptp_insert_ ts_offset[5:0]) this field specifies the offset into th e ptp header where the receive ingress time is inserted. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 010000b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 351 lan9250 14.8.25 1588 port rx filter configur ation register (1588 _rx_filter_config) this register is used to configure ptp message filtering. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 168h size: 32 bits bank: 1 bits description type default 31:19 reserved ro - 18 rx ptp alternate master filter enable (rx_ptp_alt_master_fltr_en) this bit enables message filtering based on the alternatemasterflag flagfield bit. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 17 rx ptp domain filter enab le (rx_ptp_domain_fltr_en) this bit enables message filtering based on the ptp domain. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 16 rx ptp version filter enab le (rx_ptp_version_fltr_en) this bit enables message filtering based on the ptp version. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 15:0 rx ptp message type filter enable (rx_ptp_msg_fltr_en[15:0]) these bits enable individual message filt ering. bit 0 of this field corresponds to a message type value of 0 (sync), bit 1 to message type value 1 (delay_req), etc. typically delay_req and delay_resp messages are filtered for peer-to-peer transparent clocks. r/w 0000h downloaded from: http:///
lan9250 ds00001913a-page 352 ? 2015 microchip technology inc. 14.8.26 1588 port rx ingress time sec onds register (1588_rx_ingress_sec) this read only regist er combined with the 1588 port rx ingress time nanoseconds register (1588_rx_in- gress_ns) contains the rx timestamp captures. up to four captures are buffered. note: values are only valid if the 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 16ch size: 32 bits bank: 1 bits description type default 31:0 timestamp seconds (ts_sec) this field contains the seconds portion of the receive ingress time. ro 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 353 lan9250 14.8.27 1588 port rx ingress time nano seconds register (1588_rx_ingress_ns) this read only register combined with the 1588 port rx ingress time seconds register (1588_rx_ingress_sec) contains the rx timestamp capture. up to four captures are buffered. note: values are only valid if the 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 170h size: 32 bits bank: 1 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the receive ingress time. ro 00000000h downloaded from: http:///
lan9250 ds00001913a-page 354 ? 2015 microchip technology inc. 14.8.28 1588 port rx message head er register (1588_rx_msg_header) this read only register contains the rx message header. up to four captures are buffered. note: values are only valid if the 1588 rx timestamp count (1588_rx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 174h size: 32 bits bank: 1 bits description type default 31:20 source port identity crc (src_prt_crc) this field contains the 12-bit crc of the sourceportidentity field of the received ptp packet. ro 000h 19:16 message type (msg_type) this field contains the messagetype field of the received ptp packet. ro 0h 15:0 sequence id (seq_id) this field contains the sequenceid field of the received ptp packet. ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 355 lan9250 14.8.29 1588 port rx pdelay_req ingress time seconds register (1588_rx_pdreq_sec) this register combined with the 1588 port rx pdelay_req ingress time nanoseconds register (1588_rx_p- dreq_ns) contains the ingress time of the last pdelay_req me ssage. this register is aut omatically updated if the auto update (auto) bit is set. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 178h size: 32 bits bank: 1 bits description type default 31:4 reserved ro - 3:0 timestamp seconds (ts_sec) this field contains the seconds portion of the receive ingress time. r/w 0h downloaded from: http:///
lan9250 ds00001913a-page 356 ? 2015 microchip technology inc. 14.8.30 1588 port rx pdelay_req ingress time nanoseconds register (1588_rx_pdreq_ns) this register combined with the 1588 port rx pdelay_req ingress time seconds register (1588_rx_pdreq_sec) contains the ingress time of the last pdelay_req mess age. this register is autom atically updated if the auto update (auto) bit is set. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 17ch size: 32 bits bank: 1 bits description type default 31 auto update (auto) if this bit is set, the ts_ns field in this register, the ts_sec field in 1588_rx_pdreq_sec and the cf field in 1588_rx_pdreq_cf_hi / 1588_rx_pdreq_cf_lo are updated when a pdelay_req message is received. when cleared, s/w is responsible to maintain those fields. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the receive ingress time. r/w 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 357 lan9250 14.8.31 1588 port rx pdelay_req ingr ess correction field high register (1588_rx_pdreq_cf_hi) this register combined with the 1588 port rx pdelay_req ingress corre ction field low register (1588_rx_p- dreq_cf_low) contains the correction field from the last p delay_req message. only the nanoseconds portion is used. this register is automatically updated if the auto update (auto) bit is set. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 180h size: 32 bits bank: 1 bits description type default 31:0 correction field (cf[63:32]) this field contains the upper 32 bits of the correction field. r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 358 ? 2015 microchip technology inc. 14.8.32 1588 port rx pdelay_req in gress correction field low register (1588_rx_pdreq_cf_low) this register combined with the 1588 port rx pdelay_req ingress correction field high register (1588_rx_p- dreq_cf_hi) contains the correction field from the last pdelay_req message. only the nan oseconds portion is used. this register is automatically updated if the auto update (auto) bit is set. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 184h size: 32 bits bank: 1 bits description type default 31:16 correction field (cf[31:16]) this field contains the low middle 16 bits of the correction field. r/w 0000h 15:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 359 lan9250 14.8.33 1588 port rx checks um dropped count register (1588_rx_chksum_dropped_cnt) this register counts the number of packets dropped at ingress due to a bad udp checksum. the packet will also be counted as an error by the receiving mac. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 188h size: 32 bits bank: 1 bits description type default 31:0 bad checksum dropped count (bad_chksum_dropped_cnt[31:0]) this field is a count of packets drop ped at ingress due to a bad udp check- sum. it can be cleared by writing a zero value at the risk of losing any previ- ous count. note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mbps is approximately 481 hours. r/w 00000000h downloaded from: http:///
lan9250 ds00001913a-page 360 ? 2015 microchip technology inc. 14.8.34 1588 port rx filtered count register (1588_rx_filtered_cnt) this register counts the number of pa ckets filtered at ingress due to ingress message filtering . the packet will also be counted as an error by the receiving mac. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 18ch size: 32 bits bank: 1 bits description type default 31:0 filtered count (filtered_cnt[31:0]) this field is a count of packets dropped at ingress due to ingress message filtering . it can be cleared by writing a zero value at the risk of losing any pre- vious count.note: this counter will stop at its maximum value of ffff_ffffh. minimum rollover time at 100 mb ps is approximately 481 hours. r/w 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 361 lan9250 14.8.35 1588 port tx parsi ng configuration register (1588_tx_parse_config) this register is used to configur e the ptp transmit message detection. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 158h size: 32 bits bank: 2 bits description type default 31:15 reserved ro - 14 tx layer 2 address 1 enable (tx_layer2_add1_en) this bit enables the layer 2 mac address of 01:80:c2:00:00:0e for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 13 tx layer 2 address 2 enable (tx_layer2_add2_en) this bit enables the layer 2 mac ad dress of 01:1b:19:00:00:00 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 12 tx address 1 enable (tx_add1_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:81 and ipv4 desti- nation address of 224.0.1.129 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:81 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:181 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 11 tx address 2 enable (tx_add2_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:82 and ipv4 desti- nation address of 224.0.1.130 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:82 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:182 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b downloaded from: http:///
lan9250 ds00001913a-page 362 ? 2015 microchip technology inc. 10 tx address 3 enable (tx_add3_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:83 and ipv4 desti- nation address of 224.0.1.131 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:83 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:183 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 9 tx address 4 enable (tx_add4_en) this bit enables the ipv4 mac address of 01:00:5e: 00:01:84 and ipv4 desti- nation address of 224.0.1.132 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:01:84 and ipv6 desti- nation address of ff0x:0:0:0:0:0:0:184 for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 8 tx address 5 enable (tx_add5_en) this bit enables the ipv4 mac address of 01:00:5e:00:00:6b and ipv4 desti- nation address of 224.0.0.107 for ptp packets. this bit enables the ipv6 mac address of 33:33:00:00:00:6b and ipv6 desti- nation address of ff02:0:0:0: 0:0:0:6b for ptp packets. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 7 tx user defined layer 2 mac address enable (tx_layer2_user_mac_en) this bit enables a user defined layer 2 mac address in ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 6 tx user defined ipv6 mac address enable (tx_ipv6_user_mac_en) this bit enables a user defined ipv6 mac address in ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 5 tx user defined ipv4 mac address enable (tx_ipv4_user_mac_en) this bit enables the user defined ipv4 mac address in ptp messages. the address is defined via the 1588 user mac address high-word register (1588_user_mac_hi) and the 1588 user mac address low-dword register (1588_user_mac_lo) . note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 363 lan9250 4 tx ip address enable (tx_ip_addr_en) this bit enables the checking of the ip destination address in ptp messages for both ipv4 and ipv6 formats. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 3 tx mac address enable (tx_mac_addr_en) this bit enables the checking of the mac destination address in ptp mes- sages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 2 tx layer 2 enable (tx_layer2_en) this bit enables the detection of the layer 2 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 1 tx ipv6 enable (tx_ipv6_en) this bit enables the detection of the udp/ipv6 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b 0 tx ipv4 enable (tx_ipv4_en) this bit enables the detection of the udp/ipv4 formatted ptp messages. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 1b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 364 ? 2015 microchip technology inc. 14.8.36 1588 port tx timest amp configuration register (1588_tx_timestamp_config) this register is used to configure ptp transmit message timestamping. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 15ch size: 32 bits bank: 2 bits description type default 31:24 tx ptp domain (t x_ptp_domain[7:0]) this field specifies the ptp domain in use. if tx ptp domain match enable (tx_ptp_domain_en) is set, the domainnumber in the ptp message must match the value in this field in order to recorded the egress time. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 00h 23 tx ptp domain match en able (tx_ptp_domain_en) when this bit is set, the domainnumber in the ptp message is checked against the value in tx ptp domain (t x_ptp_domain[7:0]) . note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 22 tx ptp alternate master en able (tx_ptp_alt_master_en) when this bit is set, the alternatemas terflag in the ptp message is checked for a zero value. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 21 tx ptp udp checksum check di sable (tx_ptp_udp_chksum_dis) when this bit is cleared, egress time s are not saved if the frame has an invalid udp checksum. when this bit is set, the udp checksum check is bypassed and the egress time is saved regardless. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b 20 tx ptp fcs check disa ble (tx_ptp_fcs_dis) when this bit is cleared, egress time s are not saved if the frame has an invalid fcs. when this bit is set, the fcs check is bypassed. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 365 lan9250 19:16 tx ptp version (tx_ ptp_version[3:0]) this field specifies the ptp version in use. a setting of 0 allows any ptp ver- sion. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 2h 15:0 tx ptp message type enable (tx_ptp_message_en[15:0]) these bits individually enable timestamping of their respective message types. bit 0 of this field corresponds to a message type value of 0 (sync), bit 1 to message type value 1 (delay_req), etc. typically sync, delay_req, pdelay _req and pdelay_resp messages are enabled r/w 0000h bits description type default downloaded from: http:///
lan9250 ds00001913a-page 366 ? 2015 microchip technology inc. 14.8.37 1588 port tx modifica tion register (1588_tx_mod) this register is used to configure tx ptp message modifications. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 164h size: 32 bits bank: 2 bits description type default 31:30 reserved ro - 29 tx ptp pdelay_resp message turnaround time insertion (tx_ptp_pdresp_ta_insert) note: this bit enables the turnaround time between the received pdelay_req and the transmitted pdelay_resp to be inserted into the correction field of pdelay_r esp messages sent by the host. r/w 0b 28 tx ptp sync message egress time insertion (tx_ptp_sync_ts_insert) this bit enables the egress time to be inserted into the origintimestamp field of sync messages sent by the host. r/w 0b 27:22 reserved ro - 21:16 tx ptp 1 reserved byte offset (tx_ptp_1_rsvd_offset[5:0]) this field specifies the offset into the ptp header. note: the host s/w must not change this field while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 000101b 15:0 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 367 lan9250 14.8.38 1588 port tx modification register 2 (1588_tx_mod2) this register is used to configure tx ptp message modifications. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 168h size: 32 bits bank: 2 bits description type default 31:1 reserved ro - 0 tx ptp clear udp/ipv4 checksum enable (tx_ptp_clr_udpv4_chksum) this bit enables the clearing of the udp/ipv4 checksum when pdelay_resp message turnaround time insertion or sync message egress time insertion is enabled. note: the host s/w must not change this bit while the 1588 enable (1588_enable) bit in 1588 command and control register (1588_cmd_ctl) is set. r/w 0b downloaded from: http:///
lan9250 ds00001913a-page 368 ? 2015 microchip technology inc. 14.8.39 1588 port tx egress time sec onds register (1588_tx_egress_sec) this read only register combined with the 1588 port tx egress time nanoseconds register (1588_tx_egress_ns) contains the tx timestamp captures. up to four captures are buffered. note: values are only valid if the 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 16ch size: 32 bits bank: 2 bits description type default 31:0 timestamp seconds (ts_sec) this field contains the seconds portion of the transmit egress time. ro 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 369 lan9250 14.8.40 1588 port tx egress time nano seconds register (1588_tx_egress_ns) this read only register combined with the 1588 port tx egress time seconds register (1588_tx_egress_sec) con- tains the tx timestamp capture. up to four captures are buffered. note: values are only valid if the 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 170h size: 32 bits bank: 2 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the transmit egress time. ro 00000000h downloaded from: http:///
lan9250 ds00001913a-page 370 ? 2015 microchip technology inc. 14.8.41 1588 port tx message header register (1588_tx_msg_header) this read only register contains the tx mess age header. up to four captures are buffered. note: values are only valid if the 1588 tx timestamp count (1588_tx_ts_cnt[2:0]) field indicates that at least one timestamp is available. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 174h size: 32 bits bank: 2 bits description type default 31:20 source port identity crc (src_prt_crc) this field contains the 12-bit crc of t he sourceportidentity field of the trans- mitted ptp packet. ro 000h 19:16 message type (msg_type) this field contains the messagetype field of the transmitted ptp packet. ro 0h 15:0 sequence id (seq_id) this field contains the sequenceid field of the transmitted ptp packet. ro 0000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 371 lan9250 14.8.42 1588 port tx delay_req egress ti me seconds register (1588_tx_dreq_sec) this register combined with the 1588 port tx delay_req egress time nanoseconds register (1588_tx_dreq_ns) contains the egress time of the last delay_req message. the co ntents of this field are normally only used to insert the egress time into receiv ed delay_resp messages. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 178h size: 32 bits bank: 2 bits description type default 31:4 reserved ro - 3:0 timestamp seconds (ts_sec) this field contains the seconds portion of the transmit egress time. ro 0h downloaded from: http:///
lan9250 ds00001913a-page 372 ? 2015 microchip technology inc. 14.8.43 1588 port tx delay_req egress time nanoseconds register (1588_tx_dreq_ns) this register combined with the 1588 port tx delay_req egress time seconds register (1588_tx_dreq_sec) con- tains the egress time of the last delay_req message. the cont ents of this field are normally only used to insert the egress time into receiv ed delay_resp messages. note: port and gpio registers share a common address space. port registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . offset: 17ch size: 32 bits bank: 2 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the transmit egress time. ro 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 373 lan9250 14.8.44 1588 tx one-step sy nc upper seconds register (1588_tx_one_step_sync_sec) this register contains the highest 16 bits of the originti mestamp which is inserted into sync messages when one-step timestamp insertion is enabled. note: this is a static field that is maintained by the host. it is not incremented when the lower 32 bits of the 1588 clock rollover. offset: 180h size: 32 bits bank: 2 bits description type default 31:16 reserved ro - 15:0 clock seconds high (1588_clock_sec_hi) this field contains the highest 16 bits of seconds of the 1588 clock. r/w 0000h downloaded from: http:///
lan9250 ds00001913a-page 374 ? 2015 microchip technology inc. 14.8.45 1588 gpio capture configurati on register (1588_gpio_cap_config) note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select r egister (1588_bank_port_gpio_sel) . note: the ieee 1588 unit supports 3 gpio signals. offset: 15ch size: 32 bits bank: 3 bits description type default 31:27 reserved ro - 26:24 lock enable gpio falling edge (lock_gpio_fe) these bits enable/disables the gpio falling edge lock. this lock prevents a 1588 capture from overwriting the clock value if the gpio interrupt in the 1588 interrupt status re gister (1588_int_sts) is already set due to a previ- ous capture. 0: disables gpio falling edge lock 1: enables gpio falling edge lock r/w 111b 23:19 reserved ro - 18:16 lock enable gpio rising edge (lock_gpio_re) these bits enable/disables the gpio rising edge lock. this lock prevents a 1588 capture from overwriting the clock value if the gpio interrupt in the 1588 interrupt status re gister (1588_int_sts) is already set due to a previ- ous capture. 0: disables gpio rising edge lock 1: enables gpio rising edge lock r/w 111b 15:11 reserved ro - 10:8 gpio falling edge capture enable 2-0 (gpio_fe_capture_enable[2:0]) these bits enable the falling edge of th e respective gpio input to capture the 1588 clock value and to set the respective 1588_gpio interrupt in the 1588 interrupt status regi ster (1588_int_sts) . 0: disables gpio capture 1: enables gpio capture note: the gpio must be configured as an input for this function to operate. gpio inputs are edge sensitive and must be low for greater than 40 ns to be recognized. r/w 000b 7:3 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 375 lan9250 2:0 gpio rising edge capture enable 2-0 (gpio_re_capture_enable[2:0]) these bits enable the rising edge of the respective gpio input to capture the 1588 clock value and to set the respective 1588_gpio interrupt in the 1588 interrupt status regi ster (1588_int_sts) . 0: disables gpio capture 1: enables gpio capture note: the gpio must be configured as an input for this function to operate. gpio inputs are edge sensitive and must be high for greater than 40 ns to be recognized. r/w 000b bits description type default downloaded from: http:///
lan9250 ds00001913a-page 376 ? 2015 microchip technology inc. 14.8.46 1588 gpio x rising edge clock seconds capture register (1588_gpio_re_clock_sec_cap_x) this read only regist er combined with the 1588 gpio x rising edge clock nanoseconds capture register (1588_g- pio_re_clock_ns_cap_x) forms the gpio rising edge timestamp capture. note: values are only valid if the appropriate 1588 gpio rising edge interrupt (1588_gpio_re_int[7:0]) in the 1588 interrupt status register (1588_int_sts) indicates that a timestamp is available. note: unless the corresponding lock enable gpio rising edge (lock_gpio_re) bit is set, a new capture may occur between reads of this register and the 1588 gpio x rising edge clock nanoseconds capture reg- ister (1588_gpio_re_clock_ns_cap_x) . software techniques are required to avoid reading intermedi- ate values. note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select re gister (1588_bank_port_gpio_sel) . the gpio accessed (x) is set by the gpio select (gpio_sel[2:0]) field. note: all 8 gpio register sets are available. offset: 16ch size: 32 bits bank: 3 bits description type default 31:0 timestamp seconds (ts_sec) this field contains the seconds portion of the timestamp upon the rising edge of a gpio or upon a software commanded manual capture. ro 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 377 lan9250 14.8.47 1588 gpio x rising edge cl ock nanoseconds capture register (1588_gpio_re_clock_ns_cap_x) this read only register combined with the 1588 gpio x rising edge clock second s capture register (1588_gpi- o_re_clock_sec_cap_x) forms the gpio rising edge timestamp capture. note: values are only valid if the appropriate 1588 gpio rising edge interrupt (1588_gpio_re_int[7:0]) in the 1588 interrupt status register (1588_int_sts) indicates that a timestamp is available. note: unless the corresponding lock enable gpio rising edge (lock_gpio_re) bit is set, a new capture may occur between reads of this register and the 1588 gpio x rising edge clock seconds capture register (1588_gpio_re_clock_sec_cap_x) . software techniques are required to avoid reading intermediate values. note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select re gister (1588_bank_port_gpio_sel) . the gpio accessed (x) is set by the gpio select (gpio_sel[2:0]) field. note: all 8 gpio register sets are available. offset: 170h size: 32 bits bank: 3 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds por tion of the timestamp upon the rising edge of a gpio or upon a software commanded manual capture. ro 00000000h downloaded from: http:///
lan9250 ds00001913a-page 378 ? 2015 microchip technology inc. 14.8.48 1588 gpio x falling edge clock seconds c apture register (1588_gpio_fe_clock_sec_cap_x) this read only register combined with the 1588 gpio x falling edge clock nanos econds capture register (1588_g- pio_fe_clock_ns_cap_x) forms the gpio falling edge timestamp capture. note: values are only valid if the appropriate 1588 gpio falling edge interrupt (1588_gpio_fe_int[7:0]) in the 1588 interrupt status register (1588_int_sts) indicates that a timestamp is available. note: unless the corresponding lock enable gpio falling edge (lock_gpio_fe) bit is set, a new capture may occur between reads of this register and the 1588 gpio x falling edge clock nanoseconds capture reg- ister (1588_gpio_fe_clock_ns_cap_x) . software techniques are required to avoid reading intermedi- ate values. note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select re gister (1588_bank_port_gpio_sel) . the gpio accessed (x) is set by the gpio select (gpio_sel[2:0]) field. note: all 8 gpio register sets are available. offset: 178h size: 32 bits bank: 3 bits description type default 31:0 timestamp seconds (ts_sec) this field contains the seconds portion of the timestamp upon the falling edge of a gpio or upon a software commanded manual capture. ro 00000000h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 379 lan9250 14.8.49 1588 gpio x falling edge cl ock nanoseconds capture register (1588_gpio_fe_clock_ns_cap_x) this read only register combined with the 1588 gpio x falling edge clock seconds capture register (1588_gpi- o_fe_clock_sec_cap_x) forms the gpio falling edge timestamp capture. note: values are only valid if the appropriate 1588 gpio falling edge interrupt (1588_gpio_fe_int[7:0]) in the 1588 interrupt status register (1588_int_sts) indicates that a timestamp is available. note: unless the corresponding lock enable gpio falling edge (lock_gpio_fe) bit is set, a new capture may occur between reads of this register and the 1588 gpio x falling edge clock seconds capture register (1588_gpio_fe_clock_sec_cap_x) . software techniques are required to avoid reading intermediate values. note: port and gpio registers share a common address space. gpio registers are selected by the bank select (bank_sel[2:0] in the 1588 bank port gpio select re gister (1588_bank_port_gpio_sel) . the gpio accessed (x) is set by the gpio select (gpio_sel[2:0]) field. note: all 8 gpio register sets are available. offset: 17ch size: 32 bits bank: 3 bits description type default 31:30 reserved ro - 29:0 timestamp nanoseconds (ts_ns) this field contains the nanoseconds portion of the timestamp upon the falling edge of a gpio or upon a software commanded manual capture. ro 00000000h downloaded from: http:///
lan9250 ds00001913a-page 380 ? 2015 microchip technology inc. 15.0 general purpose time r & free-running clock this chapter details the general purpos e timer (gpt) and the free-running clock. 15.1 general purpose timer the device provides a 16-bit programm able general purpose timer that can be used to generate periodic system inter- rupts. the resolution of this timer is 100 s. the gpt loads the general purpose timer count register (gpt_cnt) with the value in the general purpose timer pre-load (gpt_load) field of the general purpose timer confi guration register (gpt_cfg) when the general pur- pose timer enable (timer_en) bit of the general purpose timer configuration register (gpt_cfg) is asserted (1). on a chip-level reset or when the general purpose timer enable (timer_en) bit changes from asserted (1) to de- asserted (0), the general purpose timer pre-load (gpt_load) field is initialized to ffffh. the general purpose timer count register (gpt_cnt) is also initialized to ffffh on reset. once enabled, the gpt counts down until it reaches 0000h. at 0000h, the counter wraps around to ffffh, asserts the gp timer (gpt_int) interrupt status bit in the interrupt status register (int_sts) , asserts the irq interrupt (if gp timer interrupt enable (gpt_int_en) is set in the interrupt enable register (int_en) ) and continues counting. gp timer (gpt_int) is a sticky bit. once this bit is asserted, it can only be cleared by writing a 1 to the bit. refer to section 8.2.6, "general purpose timer interrupt," on page 65 for additional informati on on the gpt interrupt. software can write a pre-load value into the general purpose timer pre-load (gpt_load) field at any time (e.g., before or after the general purpose timer enable (timer_en) bit is asserted). the general purpose timer count reg- ister (gpt_cnt) will immediately be set to the new value and continue to count down (if enabled) from that value. 15.2 free-running clock the free-running clock (frc) is a simple 32-bit up-counter that operates from a fixed 25 mhz clock. the current frc value can be read via the free running 25mhz counter register (free_run) . on assertion of a chip-level reset, this counter is cleared to zero. on de-assertion of a reset, the counter is incr emented once for every 25 mhz clock cycle. when the maximum count has been reached, the counter rolls over to zeros. the frc does not generate interrupts. note: the free running counter can take up to 160 ns to clear after a reset event. 15.3 general purpose timer and free-running clock registers this section details the directly addressable general purpos e timer and free-running clock related system csrs. for an overview of the entire directly addressable register map, refer to section 5.0, "register map," on page 29 . table 15-1: miscellaneous registers address register name (symbol) 08ch general purpose timer conf iguration register (gpt_cfg) 090h general purpose timer count register (gpt_cnt) 09ch free running 25mhz counter register (free_run) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 381 lan9250 15.3.1 general purpose timer configuration register (gpt_cfg) this read/write register configures the devices general purpose timer (gpt). the gpt can be configured to generate host interrupts at the interval defined in this register . the current value of the gpt can be monitored via the general purpose timer count register (gpt_cnt) . refer to section 15.1, "general purpose timer," on page 380 for additional information. offset: 08ch size: 32 bits bits description type default 31:30 reserved ro - 29 general purpose timer enable (timer_en) this bit enables the gpt. when set, the gpt enters the run state. when cleared, the gpt is halted. on the 1 to 0 transition of this bit, the gpt_load field of this register will be preset to ffffh. 0: gpt disabled 1: gpt enabled r/w 0b 28:16 reserved ro - 15:0 general purpose timer pre-load (gpt_load) this value is pre-loaded into the gpt. th is is the starting value of the gpt. the timer will begin decrementing from this value when enabled. r/w ffffh downloaded from: http:///
lan9250 ds00001913a-page 382 ? 2015 microchip technology inc. 15.3.2 general purpose timer count register (gpt_cnt) this read-only register reflects the curr ent general purpose timer (gpt) value. th e register should be used in conjunc- tion with the general purpose timer configuration register (gpt_cfg) to configure and monitor the gpt. refer to section 15.1, "general purpose timer," on page 380 for additional information. offset: 090h size: 32 bits bits description type default 31:16 reserved ro - 15:0 general purpose timer current count (gpt_cnt) this 16-bit field represents the current value of the gpt. ro ffffh downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 383 lan9250 15.3.3 free running 25mhz counter register (free_run) this read-only register reflects the current va lue of the free-running 25mhz counter. refer to section 15.2, "free-run- ning clock," on page 380 for additional information. offset: 09ch size: 32 bits bits description type default 31:0 free running counter (fr_cnt) this field reflects the current value of the free-running 32-bit counter. at reset, the counter starts at zero and is incremented by one every 25 mhz cycle. when the maximum c ount has been reac hed, the counter will rollover to zero and continue counting. note: the free running counter can take up to 160ns to clear after a reset event. ro 00000000h downloaded from: http:///
lan9250 ds00001913a-page 384 ? 2015 microchip technology inc. 16.0 gpio/led controller 16.1 functional overview the gpio/led controller provides 3 confi gurable general purpose input/output pins, gpio[2:0] . these pins can be indi- vidually configured to function as inputs, push-pull outputs or open drain outputs and each is capable of interrupt gen- eration with configurable polarity. alternatively, all 3 gpio pins can be configured as led outputs, enabling these pins to drive ethernet status leds for external indication of various attributes of the port. all gpios also provide extended 1588 functionality. refer to section 14.5, "1588 gpios," on page 314 for additional details. gpio and led functionality is configured via the gpio/led system control and status registers (csrs). these reg- isters are defined in section 16.4, "gpio/led registers," on page 386 . 16.2 gpio operation the gpio controller is comprised of 3 programmable input/outpu t pins. these pins are individually configurable via the gpio csrs. on application of a chip-level reset: all gpios are set as inputs ( gpio direction 2-0 (gpiodir[2:0]) cleared in general purpose i/o data & direction register (gpio_data_dir) ) all gpio interrupts are disabled ( gpio interrupt enable[2:0] (gpio[2:0]_int_en) cleared in general purpose i/o interrupt status and enable register (gpio_int_sts_en) all gpio interrupts are configured to low logic level triggering ( gpio interrupt/1588 polari ty 2-0 (gpio_pol[2:0]) cleared in general purpose i/o configuration register (gpio_cfg) ) note: gpio[2:0] may be configured as led outputs by default, dependent on the led_en_strap[2:0] configuration straps. refer to section 16.3, "led operation" for additional information. the direction and buffer type of all gpios are configured via the general purpose i/o config uration register (gpi- o_cfg) and general purpose i/o data & direction register (gpio_data_dir) . the direction of each gpio, input or output, should be configured first via its respective gpio direction 2-0 (gpiodir[2:0]) bit in the general purpose i/o data & direction register (gpio_data_dir) . when configured as an output, the output buffer type for each gpio is selected by the gpio buffer type 2-0 (gpiobuf[2:0]) bits in the general purpose i/o configuration register (gpi- o_cfg) . push/pull and open-drain output bu ffers are supported for each gpio. when functioning as an open-drain driver, the gpio output pin is driven low when the corresponding gpio data 2-0 (gpiod[2:0]) bit in the general pur- pose i/o data & direction register (gpio_data_dir) is cleared to 0 and is not driven when set to 1. when a gpio is enabled as a push/pull output, the valu e output to the gpio pin is set via the corresponding gpio data 2-0 (gpiod[2:0]) bit in the general purpose i/o data & direction register (gpio_data_dir) . for gpios configured as inputs, the corresponding gpio data 2-0 (gpiod[2:0]) bit reflects the current state of the gpio input. in gpio mode, the input buffers are disabled when the pin is set to an output and the pull-ups are normally enabled. note: upon reset, gpios that were outputs may generate an active interrupt stat us as the system settles - typically when a low gpio pin slowly rises due to the internal pull-up. the interrupt status bits within the general purpose i/o interrupt status and enable register (gpio_int_sts_en) should be cleared as part of the device initialization software routine. 16.2.1 gpio interrupts each gpio provides the ability to trig ger a unique gpio interrupt in the general purpose i/o interrupt status and enable register (gpi o_int_sts_en) . reading the gpio interrupt[2:0] (gpio[2:0]_int) bits of this register provides the cur- rent status of the corresponding interrupt and each interrupt is enabled by setting the corresponding gpio interrupt enable[2:0] (gpio[2:0]_int_en) bit. the gpio/led controller aggregates the enabled interrupt values into an internal signal that is sent to the system inte rrupt controller and is reflected via the interrupt status register (int_sts) gpio interrupt event (gpio) bit. for more information on interrupts, refer to section 8.0, "system interrupts," on page 62 . as interrupts, gpio inputs are level sensitive and must be active for greater than 40 ns to be recognized. 16.2.1.1 gpio in terrupt polarity the interrupt polarity can be set for each individual gpio via the gpio interrupt/1588 polari ty 2-0 (gpio_pol[2:0]) bits in the general purpose i/o configuration register (gpio_cfg) . when set, a high logic level on the gpio pin will set the corresponding interrupt bit in the general purpose i/o interrupt status and enable register (gpio_int_sts_en) . when cleared, a low logic level on the gpio pin will set the corresponding interrupt bit. downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 385 lan9250 16.3 led operation gpio[2:0] can be individually selected to function as a led. these pins are configured as led outputs by setting the corresponding led enable 2-0 (led_en[2:0]) bit in the led configuration register (led_cfg) . when configured as an led, the pin is either a push-pull or open-drain / open-source output and th e gpio related input buffer and pull-up are disabled. the default configuration, including polarity, is determined by input straps or eeprom entries. refer to section 7.0, "configurat ion straps," on page 54 for additional information. the functions associated with each led pin are configurable via the led function 2-0 (led_fun[2:0]) bits of the led configuration register (led_cfg) . these bits allow the configuration of each led pin to indicate various port related functions. the behaviors of each led for each led function 2-0 (led_fun[2:0]) configuration are described in the following tables. detailed definitions for each led indication type are provided in section 16.3.1 . the default values of the led function 2-0 (led_fun[2:0]) and led enable 2-0 (led_en[2:0]) bits of the led con- figuration register (led_cfg) are determined by the led_fun_strap[2:0] and led_en_strap[2:0] configuration straps. for more information on the led configuration register (led_cfg) and its related straps, refer to section 16.4.1, "led configuration register (led_cfg)," on page 387 . all led outputs may be disabled by setting the led disable (led_dis) bit in the power management control register (pmt_ctrl) . open-drain / open-source leds are un-driven. push-pull leds are still driven but are set to their inactive state. the various led indication functions listed in the pr evious tables are described in the following section. 16.3.1 led function definitions the following led rules apply : active is defined as the pin being driven to the opposit e value latched at reset on the related hard-straps. the led polarity cannot be modified via soft-straps. inactive is defined as the pin not being driven. the input buffers and pull-ups are disabled on the shared gpio/led pins. the following led function definitions apply : activity - the signal is pulsed active for 80ms to indicate transmit or receive activity on the port. the signal is table 16-1: led operation as a function of led_fun[2:0] = 000b - 011b 000b 001b 010b 011b led2 (gpio2) link / activity 100link / activity activity activity led1 (gpio1) full-duplex / collision full-duplex / collision link link led0 (gpio0) speed 10link / activity speed full-duplex / collision table 16-2: led operation as a function of led_fun[2:0] = 100b - 111b 100b 101b 110b 111b led2 (gpio2) activity reserved reserved reserved led1 (gpio1) 10link led0 (gpio0) 100link downloaded from: http:///
lan9250 ds00001913a-page 386 ? 2015 microchip technology inc. then made inactive for a minimum of 80ms, after which t he process will repeat if rx or tx activity is again detected. note: the idle condition is inactive in contrast to that of the link / activity function. note: the signal will be held inactive if the phy does not have a valid link. link - a steady active output indicates th at the port has a valid link (10mbps or 100mbps), while a steady inactive output indicates no link on the port. link / activity - a steady active output indicate s that the port has a valid link, while a steady inactive output indi- cates no link on the port. when the port has a valid link, the signal is pulsed inactive for 80 ms to indicate transmit or receive activity on the port. the signal is then made active for a minimum of 80 ms, after which the process will repeat if rx or tx activity is again detected. 100link - a steady active output indicates the port has a va lid link and the speed is 100 mbps. the signal will be held inactive if the port does not have a valid link or the speed is not 100 mbps. 100link / activity - a steady active output indicates the port has a valid link and the speed is 100 mbps. the sig- nal is pulsed inactive for 80 ms to indicate tx or rx acti vity on the port. the signal is then driven active for a min- imum of 80 ms, after which the process will repeat if rx or tx activity is again detected. the signal will be held inactive if the port does not have a valid link or the speed is not 100 mbps. 10link - a steady active output indicates the port has a valid link and the speed is 10 mbps. this signal will be held inactive if the port does not have a valid link or the speed is not 10 mbps. 10link / activity - a steady active output indica tes the port has a valid link and the speed is 10 mbps. the signal is pulsed inactive for 80 ms to indicate transmit or receive activity on the port. the signal is then driven active for a minimum of 80 ms, after which the process will repeat if rx or tx activity is again detected. this signal will be held inactive if the port does not have a valid link or the speed is not 10 mbps. full-duplex / collision - a steady active output indicates the port is in full-duplex mode. in half-duplex mode, the signal is pulsed active for 80 ms to indicate a network co llision. the signal is then made inactive for a minimum of 80 ms, after which the process will repeat if another collision is detected. the signal will be held inactive if the port does not have a valid link. speed - a steady active output indicates a valid link with a speed of 100 mbps. a steady inactive output indicates a speed of 10 mbps. the signal will be held inactive if the port does not have a valid link. 16.4 gpio/led registers this section details the directly addressable general purpose i/o (gpio) and led related system csrs. for an over- view of the entire directly addressable register map, refer to section 5.0, "register map," on page 29 . table 16-3: gpio/led registers address register name (symbol) 1bch led configuration register (led_cfg) 1e0h general purpose i/o configuration register (gpio_cfg) 1e4h general purpose i/o data & direction register (gpio_data_dir) 1e8h general purpose i/o interrupt status and enable register (gpio_int_sts_en) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 387 lan9250 16.4.1 led configuratio n register (led_cfg) this read/write regist er configures the gpio[2:0] pins as led pins and sets their functionality. note 1: the default value of this field is determined by the configuration strap led_fun_strap[2:0] . note 2: the default value of this field is determined by the configuration strap led_en_strap[2:0] . offset: 1bch size: 32 bits bits description type default 31:11 reserved ro - 10:8 led function 2-0 (led_fun[2:0]) these bits control the function associated with each led pin as shown in section 16.3, "led operation," on page 385 . note: in order for these assignments to be valid, the particular pin must be enabled as an led output pin via the led_en bits of this register. r/w note 1 7:3 reserved ro - 2:0 led enable 2-0 (led_en[2:0]) this field toggles the functionality of the gpio[2:0] pins between gpio and led. 0: enables the associated pin as a gpio signal 1: enables the associated pin as a led output when configured as led outputs, the pins are open-drain/open-source out- puts and the pull-ups and input buffers are disabled. when open-drain/open- source, the polarity of the pins dep ends upon the strap value sampled at reset. if a high is sample d at reset, then this signal is active low. note: the polarity is determined by the strap value sampled on reset (a hard-strap) and not the soft-strap value (of the shared strap) set via eeprom. when configured as a gpio output, the pins are configured per the general purpose i/o configuration register (gpio_cfg) and the general purpose i/ o data & direction register (gpio_data_dir) . the polarity of the pins does not depend upon the strap value sampled at reset. r/w note 2 downloaded from: http:///
lan9250 ds00001913a-page 388 ? 2015 microchip technology inc. 16.4.2 general purpose i/o conf iguration register (gpio_cfg) this read/write register configures the gpio input and output pins. the pol arity of the gpio pins is configured here as well as the ieee 1588 timestamping and clo ck compare event output properties. refer to section 14.5, "1588 gpios," on page 314 for additional 1588 information. offset: 1e0h size: 32 bits bits description type default 31:27 reserved ro - 26:24 1588 gpio channel select 2-0 (gpio_ch_sel[2:0]) these bits select the 1588 channel to be output on the corresponding gpio[2:0]. refer to section 14.5, "1588 gpios," on page 314 for additional information. 0: sets 1588 channel a as the output for the corresponding gpio pin 1: sets 1588 channel b as the output for the corresponding gpio pin r/w 000b 23:19 reserved ro - 18:16 gpio interrupt/1588 polari ty 2-0 (gpio_pol[2:0]) these bits set the interrupt input polar ity and 1588 clock event output polarity of the 3 gpio pins. the configured le vel (high/low) will set the corresponding gpio_int bit in the general purpose i/o interrupt status and enable regis- ter (gpio_int_sts_en) . 1588 clock events will be output active at the con- figured level (high/low). these bits also determine the polarity of the gpio 1588 timer interrupt clear inputs. refer to section 14.5, "1588 gpios," on page 314 for additional infor- mation. 0: sets low logic level trigger on corresponding gpio pin 1: sets high logic level trigger on corresponding gpio pin r/w 000b 15:11 reserved ro - 10:8 1588 gpio output enable 2-0 (1588_gpio_oe[2:0]) these bits configure the 3 gpio pins to output 1588 clock compare events. 0: disables the output of 1588 clock compare events 1: enables the output of 1588 clock compare events note: these bits override the direction bits in the general purpose i/o data & direction register (gpio_data_dir) register. however, the gpio buffer type 2-0 (gpiobuf[2:0]) in the general purpose i/o configuration register (gpio_cfg) is not overridden. r/w 000b 7:3 reserved ro - downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 389 lan9250 2:0 gpio buffer type 2-0 (gpiobuf[2:0]) this field sets the buffer types of the 3 gpio pins. 0: corresponding gpio pin configured as an open-drain driver 1: corresponding gpio pin configured as a push/pull driver as an open-drain driver, the output pin is driven low when the corresponding data register is cleared, and is not driven when the corresponding data regis- ter is set. as an open-drain driver used for 1588 clock events, the corresponding gpio_pol_x bit determines when the corresponding pin is driven per the following table: r/w 000b bits description type default gpiox clock event polarity 1588 clock event pin state 0 no not driven 0 yes driven low 1 no driven low 1 yes not driven downloaded from: http:///
lan9250 ds00001913a-page 390 ? 2015 microchip technology inc. 16.4.3 general purpose i/o data & di rection register (gpio_data_dir) this read/write register configures the direction of the gpio pins and contains the gpio input and output data bits. offset: 1e4h size: 32 bits bits description type default 31:19 reserved ro - 18:16 gpio direction 2-0 (gpiodir[2:0]) these bits set the input/output direction of the 3 gpio pins. 0: gpio pin is configured as an input 1: gpio pin is configured as an output r/w 000b 15:3 reserved ro - 2:0 gpio data 2-0 (gpiod[2:0]) when a gpio pin is enabled as an output, the value written to this field is out- put on the corresponding gpio pin. up on a read, the value returned depends on the current direction of the pin. if the pin is an input, the data reflects the current state of the corresponding gpio pi n. if the pin is an output, the data is the value that was last written into th is register. the pin direction is deter- mined by the gpiodir bits of this re gister and the 1588_gpio_oe bits in the general purpose i/o configuration register (gpio_cfg) . r/w 000b downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 391 lan9250 16.4.4 general purpose i/o interr upt status and enable register (gpio_int_sts_en) this read/write register contains the gpio interrupt status bits. writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. if enabled, these interrupt bits are cascaded into the gpio interrupt event (gpio) bit of the interrupt status register (int_sts) . writing a 1 to any of the interrupt enable bits will enable the corresponding interrupt as a source. status bits will still reflect the status of the int er- rupt source regardless of whether the source is enabled as an interrupt in this register. the gpio interrupt event enable (gpio_en) bit of the interrupt enable register (int_en) must also be set in order for an actual system level interrupt to occur. refer to section 8.0, "system interrupts," on page 62 for additional information. offset: 1e8h size: 32 bits bits description type default 31:19 reserved ro - 18:16 gpio interrupt enable[2 :0] (gpio[2:0]_int_en) when set, these bits enable the corresponding gpio interrupt. note: the gpio interrupts must also be enabled via the gpio interrupt event enable (gpio_en) bit of the interrupt enable register (int_en) in order to cause the interrupt pin ( irq ) to be asserted. r/w 000b 15:3 reserved ro - 2:0 gpio interrupt[2:0] (gpio[2:0]_int) these signals reflect the interrupt stat us as generated by the gpios. these interrupts are configured through the general purpose i/o configuration register (gpio_cfg) . note: as gpio interrupts, gpio inputs are level sensitive and must be active greater than 40 ns to be recognized as interrupt inputs. r/wc 000b downloaded from: http:///
lan9250 ds00001913a-page 392 ? 2015 microchip technology inc. 17.0 miscellaneous this chapter describes miscellaneous functions an d registers that are present in the device. 17.1 miscellaneous system configuration & status registers this section details the remainder of the directly addre ssable system csrs. these registers allow for monitoring and configuration of various device functions such as the chip id/revision, byte order testi ng, and hardware configuration. for an overview of the entire directly addressable register map, refer to section 5.0, "register map," on page 29 . table 17-1: miscellaneous registers address register name (symbol) 050h chip id and revision (id_rev) 064h byte order test register (byte_test) 074h hardware configuration register (hw_cfg) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 393 lan9250 17.1.1 chip id and revision (id_rev) this read-only register contains the id and revision fields for the device. note 1: default value is dependent on device revision. offset: 050h size: 32 bits bits description type default 31:16 chip id this field indicates the chip id. ro 9250 15:0 chip revision this field indicates the design revision. ro note 1 downloaded from: http:///
lan9250 ds00001913a-page 394 ? 2015 microchip technology inc. 17.1.2 byte order test register (byte_test) this read-only register can be used to determine the byte ordering of the current configuration. byte ordering is a func- tion of the host data bus width and endianess. refer to section 9.0, "host bus interface," on page 74 for additional infor- mation on byte ordering. the byte_test register can optionally be used as a dumm y read register when assuring minimum write-to-read or read-to-read timing. refer to section 9.0, "host bus interface," on page 74 for additional information. for host interfaces that are disabled during the reset state, the byte_test register can be used to determine when the device has exited the reset state. note: this register can be read while the device is in the re set or not ready / power savings states without leaving the host interface in an intermediate state. if the ho st interface is in a reset state, returned data may be invalid. however, during reset, the returned data will not match the normal valid data pattern. note: it is not necessary to read all fours bytes of this r egister. dword access rules do not apply to this register. offset: 064h size: 32 bits bits description type default 31:0 byte test (byte_test) this field reflects the current byte ordering ro 87654321h downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 395 lan9250 17.1.3 hardware configuration register (hw_cfg) this register allows the configuration of various hardware features including tx/rx fifo sizes and host mac transmit threshold properties. a detailed explanation of the allow able settings for fifo memory allocation can be found in sec- tion 11.10.3, "fifo memory allocation configuration," on page 157 . note: this register can be read while the device is in the re set or not ready / power savings states without leaving the host interface in an intermediate state. if the ho st interface is in a reset state, returned data may be invalid. note: it is not necessary to read all fours bytes of this r egister. dword access rules do not apply to this register. offset: 074h size: 32 bits bits description type default 31:28 reserved ro - 27 device ready (ready) when set, this bit indicates that the device is ready to be accessed. upon power-up, rst# reset, return from power savings states, host mac module level reset or digital reset, the host processor may interrogate this field as an indication that the device has stabilized and is fully active. this rising edge of this bit will assert the device ready (ready) bit in the interrupt status register (int_sts) and can cause an interrupt if enabled. note: with the exception of the hw_cfg, pmt_ctrl, byte_test, and reset_ctl registers, read access to any internal resources is forbidden while the ready bit is cleared. writes to any address are invalid until this bit is set. note: this bit is identical to bit 0 of the power management control register (pmt_ctrl) . ro 0b 26 reserved ro - 25 amdix_en strap state this bit reflects the state of the aut o_mdix_strap_1 strap that connects to the phy. the strap value is loaded with the level of the auto_mdix_strap_1 during reset and can be re-written by the eeprom loader. the strap value can be overridden by bit 15 and 13 of the phy special control/status indica- tion register (phy_special_control_stat_ind) . ro note 2 24:22 reserved ro - 21 reserved - this bit must be writte n with 0b for pr oper operation. r/w 0b 20 must be one (mbo). this bit must be set to 1 for normal device operation. r/w 0b downloaded from: http:///
lan9250 ds00001913a-page 396 ? 2015 microchip technology inc. note 2: the default value of this field is de termined by the configuration strap auto_mdix_strap_1 . see section 6.3, "power management," on page 44 for more information. 19:16 tx fifo size (tx_fif_sz) this field sets the size of the tx fifo s in 1kb values to a maximum of 14kb. the tx status fifo consumes 512 bytes of the space allocated by tx_fif_- siz, and the tx data fi fo consumes the remaining space specified by tx_fif_sz. the minimum size of the tx fifos is 2kb (tx data fifo and status fifo combined). the tx data fifo is used for both tx data and tx commands. the rx status and data fifos cons ume the remaining space, which is equal to 16kb minus tx_fif_siz. see section section 11.10.3, "fifo mem- ory allocation configuration," on page 157 for more information. r/w 5h 15:14 reserved ro - 13:12 reserved - this field must be wri tten with 00b for proper operation. r/w 00b 11:0 reserved ro - bits description type default downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 397 lan9250 18.0 jtag 18.1 jtag a ieee 1149.1 compliant tap controller suppor ts boundary scan and various test modes. the device includes an integrated jtag boundary-scan test por t for board-level testing. the interface consists of four pins ( tdo , tdi , tck and tms ) and includes a state machine, data register array, and an instruction register. the jtag pins are described in table 3-9, jtag pin descriptions, on page 25 . the jtag interface conforms to the ieee stan- dard 1149.1 - 2001 standard test access port (tap) and boundary-scan architecture . all input and output data is synchronous to the tck test clock input. tap input signals tms and tdi are clocked into the test logic on the rising edge of tck , while the output signal tdo is clocked on the falling edge. jtag pins are multiplexed with th e gpio/led and eeprom pins. the jtag functionality is selected when the test- mode pin is asserted. the implemented ieee 1149.1 instructions and their op codes are shown in ta b l e 1 8 - 1 . note: the jtag device id is 000f1445h note: all digital i/o pins support ieee 1149.1 operation. analog pins and the osci / osco pins do not support ieee 1149.1 operation. table 18-1: ieee 1149.1 op codes instruction op code comment bypass 0 16'h0000 mandatory instruction bypass 1 16'hffff mandatory instruction sample/preload 16'hfff8 mandatory instruction extest 16'hffe8 mandatory instruction clamp 16'hffef optional instruction id_code 16'hfffe optional instruction highz 16'hffcf optional instruction int_dr_sel 16'hfffd private instruction downloaded from: http:///
lan9250 ds00001913a-page 398 ? 2015 microchip technology inc. 18.1.1 jtag timing requirements this section specifies the jtag timing of the device. note: timing values are with respect to an equivalent test load of 25 pf. figure 18-1: jtag timing table 18-2: jtag timing values symbol description min max units notes t tckp tck clock period 40 ns t tckhl tck clock high/low time t tckp *0.4 t tckp *0.6 ns t su tdi , tms setup to tck rising edge 5 ns t h tdi , tms hold from tck rising edge 5 ns t dov tdo output valid from tck falling edge 15 ns t doinvld tdo output invalid from tck falling edge 0 ns tck (input) tdi , tms (inputs) t tckhl t tckp t tckhl t su t h t dov tdo (output) t doinvld downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 399 lan9250 19.0 operational characteristics 19.1 absolute maximum ratings* supply voltage ( vdd12tx1 , vdd12tx2 , oscvdd12 , vddcr ) ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +1.5 v supply voltage ( vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 , vddio ) ( note 1 ) . . . . . . . . . . . . . 0 v to +3.6 v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to +3.6 v positive voltage on input signal pins, with respect to ground ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . vddio + 2.0 v negative voltage on input signal pins, with respect to ground ( note 3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v positive voltage on osci , with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.6 v storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 hbm esd performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . jedec class 3a note 1: when powering this device from laboratory or system powe r supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exis ts, it is suggested to use a clamp circuit. note 2: this rating does not apply to the following pins: osci , rbias note 3: this rating does not apply to the following pins: rbias *stresses exceeding those listed in th is section could cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 19.2, "operating conditions**" , section 19.5, "dc specifications" , or any other applicable section of this specif ication is not implied. note, device signals are not 5 volt tolerant. 19.2 operating conditions** supply voltage ( vdd12tx1 , vdd12tx2 , oscvdd12 , vddcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14 v to +1.26 v analog port supply voltage ( vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 ) . . . . . . . . . . . . . . . +3.0 v to +3.6 v i/o supply voltage ( vddio ) ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.62 v to +3.6 v ethernet magnetics supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25 v to +3.6 v ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 4 note 4: 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version, -40 o c to +105 o c for extended industrial version. extended industrial temperature range is supported with the following restrictions: - 64-qfn package: external regulator required (internal regulator disabled) and 2.5 v (typ) ethernet magnetics voltage. **proper operation of the device is guar anteed only within the ranges specified in this section. after the device has com- pleted power-up, vddio and the magnetics power supply must maintain their voltage level with 10%. varying the volt- age greater than 10% after the device has completed power-up can cause errors in device operation. note: do not drive input signals without power supplied to the device. downloaded from: http:///
lan9250 ds00001913a-page 400 ? 2015 microchip technology inc. 19.3 package thermal specifications note: thermal parameters are measured or estimated fo r devices in a multi-layer 2s2p pcb per jesdn51. 19.4 current consumption and power consumption this section details the devices typical supply cu rrent consumption and power di ssipation for 10base-t, 100base-tx and power management modes of operation with the internal regulator enabled and disabled. table 19-1: 64-pin qfn package thermal parameters parameter symbol value units comments thermal resistance junction to ambient ? ja 23.6 c/w measured in still air thermal resistance junction to bottom of case ? jt 0.1 c/w measured in still air thermal resistance junction to top of case ? jc 1.8 c/w airflow 1 m/s table 19-2: 64-pin tqfp-ep package thermal parameters parameter symbol value units comments thermal resistance junction to ambient ? ja 29.0 c/w measured in still air thermal resistance junction to bottom of case ? jt 0.3 c/w measured in still air thermal resistance junction to top of case ? jc 12.8 c/w airflow 1 m/s table 19-3: maximum power dissipation mode maximum power (mw) internal regulator disabled , 2.5 v ethernet magnetics 460 internal regulator disabled , 3.3 v ethernet magnetics 550 internal regulator enabled, 2.5 v ethernet magnetics 617 internal regulator enabled, 3.3 v ethernet magnetics 706 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 401 lan9250 19.4.1 internal regulator disabled table 19-4: current consumption and po wer dissipation (regs. disabled) 3.3 v device current (ma) (a) note 5 , note 7 1.2 v device current (ma) (b) note 6 , note 7 tx magnetics current (ma) (c) note 8 device power with 2.5 v magnetics (mw) note 9 , note 10 device power with 3.3 v magnetics (mw) note 9 , note 11 reset ( rst#) typ. 23.2 37.0 0.0 121 121 d0, 100base-tx with traffic (no eee) typ. 44.2 51.7 41.0 311 344 d0, 100base-tx idle (w/o eee) typ. 44.2 51.0 41.0 310 343 d0, 100base-tx idle (with eee) typ. 36.2 46.0 0.0 175 175 d0, 10base-t with traffic typ. 21.7 42.8 101.0 376 457 d0, 10base-t idle typ. 22.8 43.0 101.0 380 461 d0, phy energy detect power down typ. 8.9 40.2 0.0 78 78 d0, phy general power down typ. 4.9 40.5 0.0 65 65 d1, 100base-tx idle (w/o eee) typ. 38.1 28.6 41.0 263 296 d1, 100base-tx idle (with eee) typ. 36.6 23.3 0.0 149 149 d1, 10base-t idle typ. 16.7 19.9 101.0 332 413 d1, phy energy detect power down typ. 9.0 17.5 0.0 51 51 d1, phy general power down typ. 5.8 17.5 0.0 41 41 d2, 100base-tx idle (w/o eee) typ. 38.0 28.7 41.0 263 296 d2, 100base-tx idle (with eee) typ. 36.6 23.4 0.0 149 149 d2, 10base-t idle typ. 16.8 19.9 101.0 332 413 downloaded from: http:///
lan9250 ds00001913a-page 402 ? 2015 microchip technology inc. note 5: vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 , vddio note 6: vdd12tx1 , vdd12tx2 , oscvdd12 , vddcr note 7: current measurements do not include power applied to the magnetics or the optional external leds. note 8: the ethernet component current is independent of the supply rail voltage (2.5v or 3.3v) of the transformer. copper tp operation is assumed. current is zero if using 100base-fx mode. note 9: this includes the power dissipated by the transmit ter by way of the current through the transformer. note 10: 3.3*(a) + 1.2*(b) + (2.5)*(c) @ typ note 11: 3.3*(a) + 1.2*(b) + (3.3)*(c) @ typ 19.4.2 internal regulator enabled d2, phy energy detect power down typ. 8.7 6.1 0.0 36 36 d2, phy general power down typ. 5.9 6.1 0.0 27 27 d3, phy general power down typ. 5.7 2.7 0.0 23 23 table 19-5: current consumption and power dissipation (regs. enabled) 3.3 v device current (ma) (a) note 12 , note 13 , note 14 tx magnetics current (ma) (c) note 15 device power with 2.5 v magnetics (mw) note 16 , note 17 device power with 3.3 v magnetics (mw) note 16 , note 18 reset ( rst#) typ. 61.5 0.0 203 203 d0, 100base-tx with traffic (no eee) typ. 95.9 41.0 419 452 d0, 100base-tx idle (w/o eee) typ. 96.4 41.0 421 454 d0, 100base-tx idle (with eee) typ. 82.2 0.0 272 272 d0, 10base-t with traffic typ. 67.5 101.0 476 557 d0, 10base-t idle typ. 67.7 101.0 476 557 d0, phy energy detect power down typ. 51.4 0.0 170 170 table 19-4: current consumption and po wer dissipation (regs. disabled) downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 403 lan9250 note 12: vdd33txrx1 , vdd33txrx2 , vdd33bias , vdd33 , vddio note 13: vdd12tx1 and vdd12tx2 , are driven by the internal regulator via the pcb. the current is accounted for via vdd33 . note 14: current measurements do not include power applied to the magnetics or the optional external leds. note 15: the ethernet component current is independent of the supply rail voltage (2.5v or 3.3v) of the transformer. copper tp operation is assumed. current is zero if using 100base-fx mode. note 16: this includes the power dissipated by the transmit ter by way of the current through the transformer. note 17: 3.3*(a) + (2.5)*(c) @ typ note 18: 3.3*(a) + (3.3)*(c) @ typ d0, phy general power down typ. 48.4 0.0 160 160 d1, 100base-tx idle (w/o eee) typ. 66.6 41.0 323 356 d1, 100base-tx idle (with eee) typ. 59.2 0.0 196 196 d1, 10base-t idle typ. 38.5 101.0 380 461 d1, phy energy detect power down typ. 27.5 0.0 91 91 d1, phy general power down typ. 24.3 0.0 81 81 d2, 100base-tx idle (w/o eee) typ. 66.4 41.0 322 355 d2, 100base-tx idle (with eee) typ. 59.4 0.0 196 196 d2, 10base-t idle typ. 38.4 101.0 380 460 d2, phy energy detect power down typ. 16.2 0.0 54 54 d2, phy general power down typ. 13.3 0.0 44 44 d3, phy general power down typ. 9.4 0.0 32 32 table 19-5: current consumption and power dissipation (regs. enabled) downloaded from: http:///
lan9250 ds00001913a-page 404 ? 2015 microchip technology inc. 19.5 dc specifications table 19-6: non-variable i/o dc electrical characteristics parameter symbol min typ max units notes is type input buffer low input level high input level schmitt trigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vdd33 ) input capacitance pull-up impedance (v in = vss ) pull-down impedance (v in = vdd33 ) v ili v ihi v hys i ih c in r dpu r dpd -0.3 2.0 121 -10 6 52 0.83.6 151 10 3 8.9 79 vv mv a pf k ? k ? note 19 ai type input buffer ( fxsdena ) low input level high input level v il v ih -0.3 1.2 0.8 vdd33 +0.3 vv ai type input buffer ( rxpa/rxna) differential input level common mode voltage input capacitance v in-diff v cm c in 0.11.0 vdd33txrx1 - 1.3 vdd33txrx1 5 vv pf ai type input buffer ( fxlosen input) state a threshold state b threshold v tha v thb -0.3 1.2 0.8 vdd33 + 0.3 vv iclk type input buffer ( osci input) low input level high input level input leakage v ili v ihi i ilck -0.3 oscvdd12 -0.35 -10 0.35 3.6 10 vv a note 20 ilvpecl input buffer low input level high input level v il - vdd33txrx1 v ih - vdd33txrx1 vdd33txrx1 + 0.3 -1.14 -1.48 0.3 vv note 21 note 21 downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 405 lan9250 note 19: this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resis- tors add +/- 50 a per-pin (typical). note 20: osci can optionally be driven from a 25 mhz singled-ended clock oscillator. note 21: lvpecl compatible. note 22: v offset is a function of the external resistor network co nfiguration. the listed value is recommended to pre- vent issues due to crosstalk. olvpecl output buffer low output level high output level peak-to-peak differential (sff mode) peak-to-peak differential (sfp mode) common mode voltage offset voltage load capacitance v ol v oh v diff-sff v diff-sfp v cm v offset c load vdd33txrx1 - 1.025 1.20.6 1.0 1.6 0.8 vdd33txrx1 - 1.3 40 vdd33txrx1 - 1.62 2.01.0 10 vv v v v mv pf note 22 table 19-6: non-variable i/o dc electrical characteristics (continued) parameter symbol min typ max units notes downloaded from: http:///
lan9250 ds00001913a-page 406 ? 2015 microchip technology inc. table 19-7: variable i/o dc electrical characteristics parameter symbol min 1.8 v typ 3.3 v typ max units notes vis type input buffer low input level high input level negative-going threshold positive-going threshold schmitt trigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vddio ) input capacitance pull-up impedance (v in = vss ) pull-up current (v in = vss ) pull-down impedance (v in = vdd33 ) pull-down current (v in = vdd33 ) v ili v ihi v ilt v iht v hys i ih c in r dpu i dpu r dpd i dpd -0.3 0.640.81 102 -10 5420 54 19 0.83 0.99 158 6827 68 26 1.411.65 138 8267 85 66 3.6 1.761.90 288 10 2 vv v v mv a pf k ? a k ? a schmitt trigger schmitt trigger note 23 vo8 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 8 ma i oh = -8 ma vod8 type buffer low output level v ol 0.4 v i ol = 8 ma vo12 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 12 ma i oh = -12 ma vod12 type buffer low output level v ol 0.4 v i ol = 12 ma vos12 type buffers high output level v oh vddio - 0.4 v i oh = -12 ma vo16 type buffers low output level high output level v ol v oh vddio - 0.4 0.4 v v i ol = 16 ma i oh = -16 ma downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 407 lan9250 note 23: this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resis- tors add 50 a per-pin (typical). note 24: measured at line side of transformer, line replaced by 100 ? (+/- 1%) resistor. note 25: offset from 16 ns pulse width at 50% of pulse peak. note 26: measured differentially. note 27: min/max voltages guaranteed as measured with 100 ? resistive load. table 19-8: 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 - 1050 mvpk note 24 peak differential output voltage low v ppl -950 - -1050 mvpk note 24 signal amplitude symmetry v ss 98 - 102 % note 24 signal rise and fall time t rf 3.0 - 5.0 ns note 24 rise and fall symmetry t rfs --0 . 5n s note 24 duty cycle distortion d cd 35 50 65 % note 25 overshoot and undershoot v os --5% jitter - - - 1.4 ns note 26 table 19-9: 10base-t tran sceiver characteristics parameter symbol min typ max units notes transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 27 receiver differential squelch threshold v ds 300 420 585 mv downloaded from: http:///
lan9250 ds00001913a-page 408 ? 2015 microchip technology inc. 19.6 ac specifications this section details the various ac timing specifications of the device. note: the i 2 c timing adheres to the nxp i 2 c-bus specification . refer to the nxp i 2 c-bus specification for detailed i 2 c timing information. note: the mii/smi timing adheres to the ieee 802.3 specification . note: the rmii timing adheres to the rmii consortium rmii specification r1.2 . 19.6.1 equivalent test load output timing specifications assume the 25 pf equivalent test load, unless otherwise noted, as illustrated in figure 19-1 . figure 19-1: output equivalent test load 25 pf output downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 409 lan9250 19.6.2 power sequencing timing these diagrams illustrates the device power sequencing requirements. the vddio , vdd33 , vdd33txrx1 , vdd33txrx2 , vdd33bias and magnetics power supplies must all reach operational levels within the specified time period t pon . when operating with the internal regulators disabled, vddcr , oscvdd12 , vdd12tx1 and vdd12tx2 are also included into this requirement. in addition, once the vddio power supply reaches 1.0 v, it must reach 80% of its operating voltage level (1.44 v when operating at 1.8 v, 2.0 v when operating at 2.5 v, 2.64 v when operating at 3.3 v) within an additional 15ms. this requirement can be safely ignored if using an external reset as shown in section 19.6.3, "reset and configuration strap timing" . device power supplies can turn off in any order provided they all reach 0 volts within the specified time period t poff . figure 19-2: power sequence timing - internal regulators figure 19-3: power sequence timing - external regulators table 19-10: power sequencing timing values symbol description min typ max units t pon power supply turn on time - - 50 ms t poff power supply turn off time - - 500 ms vddio magnetics power t pon t poff vdd33 , vdd33bias , vdd33txrx1 , vdd33txrx2 vddio magnetics power t pon t poff vdd33 , vdd33bias , vdd33txrx1 , vdd33txrx2 vddcr , oscvdd12 , vdd12tx1 , vdd12tx2 downloaded from: http:///
lan9250 ds00001913a-page 410 ? 2015 microchip technology inc. 19.6.3 reset and configuration strap timing this diagram illustrates the rst# pin timing requirements and its relation to the configuration strap pins and output drive. assertion of rst# is not a requirement. however, if used, it must be asserted for the minimum period specified. the rst# pin can be asserted at any ti me, but must not be deasserted until t purstd after all external power supplies have reached operational levels. refer to section 6.2, "resets," on page 38 for additional information. note: the clock input must be stable prior to rst# deassertion. note: device configuration straps are latched as a result of rst# assertion. refer to section 6.2.1, "chip-level resets," on page 39 for details. note: configuration strap latching and output drive timings shown assume that the power-on reset has finished first otherwise the timings in section 19.6.4, "power-on and configuration strap timing" apply. figure 19-4: rst# pin configuration strap latching timing table 19-11: rst# pin configuration strap latching timing values symbol description min typ max units t purstd external power supplies at operational level to rst# deasser- tion 25 ms t rstia rst# input assertion time 200 - - ? s t css configuration strap pins setup to rst# deassertion 200 - - ns t csh configuration strap pins hold after rst# deassertion 10 - - ns t odad output drive after deassertion 3 - - us t css rst# configuration strap pins t rstia t csh output drive t odad ? ? all external power supplies t purstd v opp downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 411 lan9250 19.6.4 power-on and conf iguration strap timing this diagram illustrates the configurati on strap valid timing requirements in relation to power-on. in order for valid con- figuration strap values to be read at power-on, the following timing requirements must be met. note: configuration straps must only be pulled high or low. configuration straps must not be driven as inputs. device configuration straps are also latched as a result of rst# assertion. refer to section 19.6.3, "r eset and config- uration strap timing" and section 6.2.1, "chip-level resets," on page 39 for additional details. figure 19-5: power-on configura tion strap latching timing table 19-12: power-on configuration strap latching timing values symbol description min typ max units t cfg configuration strap valid time - - 15 ms all external power supplies configuration straps t cfg vopp downloaded from: http:///
lan9250 ds00001913a-page 412 ? 2015 microchip technology inc. 19.6.5 host bus in terface i/o timing timing specifications for the host bus interface are given in section 9.4.5, "multiplexed addressing mode timing requirements," on page 90 and section 9.5.7, "indexed addressing mode timing requirements," on page 115 . 19.6.6 spi/sqi slave interface i/o timing timing specifications for the spi/sqi slave bus interface are given in section 10.4, "spi/sqi timing requirements," on page 138 . 19.6.7 i 2 c eeprom i/o timing timing specifications for i 2 c eeprom access are given in section 13.3, "i2c master eeprom controller," on page 283 . 19.6.8 jtag timing timing specifications for the jtag interface are given in table 18.1.1, jtag timing requirements, on page 398 . downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 413 lan9250 19.7 clock circuit the device can accept either a 25 mhz crystal or a 25 mhz si ngle-ended clock oscillator (50 ppm) input. if the single- ended clock oscillator method is implemented, osco should be left unconnected and osci should be driven with a clock signal that adheres to the specifications outlined throughout section 19.0, "operational characteristics" . see table 19-13 for the recommended crystal specifications. note 28: the maximum allowable values for frequency tolerance and frequency stability are application dependent. since any particular application must meet the ieee 50 ppm total ppm budge t, the combination of these two values must be approximately 45 ppm (allowing for aging). note 29: frequency deviation over time is also referred to as aging. note 30: the total deviation for 100base-tx is 50 ppm. note 31: the minimum drive level requirement p w is reduced to 100 uw with the addition of a 500 ? series resistor, if c o ? 5pf, c l ? 12 pf and r1 ? 80 ? note 32: 0 c for commercial version, -40 c for industrial and extended industrial versions note 33: +70 c for commercial version, +85 c for industrial version, +105 c for extended industrial version note 34: this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the osci pin, osco pin and pcb capacitance values are required to accurately calculate the value of the two external load capacitors. the total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 mhz. table 19-13: crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz 802.3 frequency tolerance at 25 o c f tol - - 40 ppm note 28 802.3 frequency stability over te m p f temp - - 40 ppm note 28 802.3 frequency deviation over time f age - 3 to 5 - ppm note 29 802.3 total allowable ppm bud- get - - 50 ppm note 30 shunt capacitance c o --7p f load capacitance c l - - 18 pf drive level p w 300 note 31 -- w equivalent series resistance r 1 --1 0 0 ? operating temperature range note 32 - note 33 o c osci pin capacitance - 3 typ - pf note 34 osco pin capacitance - 3 typ - pf note 34 downloaded from: http:///
lan9250 ds00001913a-page 414 ? 2015 microchip technology inc. 20.0 package outlines 20.1 64-qfn figure 20-1: 64-qfn package downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 415 lan9250 figure 20-2: 64-qfn package dimensions downloaded from: http:///
lan9250 ds00001913a-page 416 ? 2015 microchip technology inc. 20.2 64-tqfp-ep figure 20-3: 64-tqfp-ep package downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 417 lan9250 21.0 revision history table 21-1: revision history revision level section/figure/entry correction ds00001913a (06-30-15) initial release downloaded from: http:///
lan9250 ds00001913a-page 418 ? 2015 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchips customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
? 2015 microchip technology inc. ds00001913a-page 419 lan9250 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . device: lan9250 tape and reel option: blank = standard packaging (tray) t = tape and reel ( note 1 ) temperature range: blank = 0 ? c to +70 ? c (commercial) i= - 4 0 ? c to +85 ? c (industrial) v= - 4 0 ? c to +105 ? c (extended industrial) ( note 2 ) package: ml = 64-pin qfn pt = 64-pin tqfp-ep examples: a) lan9250/ml standard packaging (tray), commercial temperature, 64-pin qfn b) lan9250ti/pt tape and reel industrial temperature, 64-pin tqfp-ep note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. 2: extended industrial temp. support (105 o c) in the 64-qfn only part no. device tape and reel option / temperature range xx [x] [x] package downloaded from: http:///
lan9250 ds00001913a-page 420 ? 2015 microchip technology inc. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breac h the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner ou tside the operating specifications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with y our specifications. microchip make s no representations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising fr om this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, i ndemnify and hold harmless microchip from any and all dama ges, claims, suits, or expenses resulting from such use. no licenses are conveyed, implic- itly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip l ogo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technol ogy incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technol ogy incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet l ogo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem .net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewsp an, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademark of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., i n other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 9781632772152 microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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